Search results for "fpga"
showing 10 items of 129 documents
A Programmable Networked Processing Node for 3D Brain Vessels Reconstruction
2011
Real-time 3D imaging represents a developing trend in medical imaging. However, most of the 3D medical imaging algorithms are computationally intensive. In this paper, a programmable networked node for 3D brain vessels reconstruction is proposed. Starting from 2D PC-MRA (Phase-Contrast Magnetic Resonance Angiography) sequences, the node is able to generate the 3D brain vasculature using the MIP (Maximum Intensity Projection) algorithm. The node has been prototyped on the Celoxica RC203E board, equipped with a Virtex II FPGA, to get the advantages of an hardware implementation, reaching a better throughput with respect to analogous software implementations. Its generality and programmable ca…
The Mu3e Data Acquisition
2020
The Mu3e experiment aims to find or exclude the lepton flavour violating decay $\mu^+\to e^+e^-e^+$ with a sensitivity of one in 10$^{16}$ muon decays. The first phase of the experiment is currently under construction at the Paul Scherrer Institute (PSI, Switzerland), where beams with up to 10$^8$ muons per second are available. The detector will consist of an ultra-thin pixel tracker made from High-Voltage Monolithic Active Pixel Sensors (HV-MAPS), complemented by scintillating tiles and fibres for precise timing measurements. The experiment produces about 100 Gbit/s of zero-suppressed data which are transported to a filter farm using a network of FPGAs and fast optical links. On the filte…
Design exploration of aes accelerators on FPGAS and GPUs
2017
The embedded systems are increasingly becoming a key technological component of all kinds of complex tech-nical systems and an exhaustive analysis of the state of the art of all current performance with respect to architectures, design methodologies, test and applications could be very in-teresting. The Advanced Encryption Standard (AES), based on the well-known algorithm Rijndael, is designed to be easily implemented in hardware and software platforms. General purpose computing on graphics processing unit (GPGPU) is an alternative to recongurable accelerators based on FPGA devices. This paper presents a direct comparison between FPGA and GPU used as accelerators for the AES cipher. The res…
Switching Frequency Effects on the Efficiency and Harmonic Distortion in a Three-Phase Five-Level CHBMI Prototype with Multicarrier PWM Schemes: Expe…
2022
The current climatic scenario requires the use of innovative solutions to increase the production of electricity from renewable energy sources. Multilevel Power Inverters are a promising solution to improve the penetration of renewable energy sources into the electrical grid. Moreover, the performance of MPIs is a function of the modulation strategy employed and of its features (modulation index and switching frequency). This paper presents an extended and experimental analysis of three-phase five-level Cascaded H-Bridges Multilevel Inverter performance in terms of efficiency and harmonic content considering several MC PWM modulation strategies. In detail, the CHBMI performance is analyzed …
Field Oriented Control of IPMSM Fed by Multilevel Cascaded H-Bridges Inverter with NI-SOM sbRIO-9651 FPGA controller
2022
Electrical drives fed by Multilevel Inverters (MIs) are of considerable interest for traction and e-mobility applications. In detail, Cascaded H-Bridge Multilevel Inverter (CHBMI) is a promising solution for electrical drive optimization purposes in terms of efficiency, safety, integration and flexible use of energy sources. The aim of this paper is the experimental implementation of the field-oriented control strategy of Interior Permanent Magnet Synchronous Machine (IPMSM) fed by CHBMI by use of NI-SOM sbrRIO-9651 FPGA controller. This FPGA controller can be programmable in the LabVIEW programming environment with the consequent benefits of graphical programming. The paper address the acq…
A Hardware and Secure Pseudorandom Generator for Constrained Devices
2018
Hardware security for an Internet of Things or cyber physical system drives the need for ubiquitous cryptography to different sensing infrastructures in these fields. In particular, generating strong cryptographic keys on such resource-constrained device depends on a lightweight and cryptographically secure random number generator. In this research work, we have introduced a new hardware chaos-based pseudorandom number generator, which is mainly based on the deletion of an Hamilton cycle within the $N$ -cube (or on the vectorial negation), plus one single permutation. We have rigorously proven the chaotic behavior and cryptographically secure property of the whole proposal: the mid-term eff…
Optimisation et implémentation de méthodes bio-inspirées d'extraction de caractéristiques pour la reconnaissance d'objets visuels
2016
Industry has growing needs for so-called “intelligent systems”, capable of not only ac-quire data, but also to analyse it and to make decisions accordingly. Such systems areparticularly useful for video-surveillance, in which case alarms must be raised in case ofan intrusion. For cost saving and power consumption reasons, it is better to perform thatprocess as close to the sensor as possible. To address that issue, a promising approach isto use bio-inspired frameworks, which consist in applying computational biology modelsto industrial applications. The work carried out during that thesis consisted in select-ing bio-inspired feature extraction frameworks, and to optimize them with the aim t…
A Novel Architecture for Inter-FPGA Traffic Collision Management
2014
International audience; —with the increasing complexity of various communi-cations and applications, Network-On-Chip (NoC) is one of the most efficient communication structures. Multi-FPGA platforms are considered as the most appropriate experimental solutions to emulate a large size of MPSoCs (Multi-Processor System-on-Chip) based on a NoC. The deployment of the NoC into several FPGAs requires the use of inter-FPGA communication links. The number and performance of external links restrict the bandwidth of communication. Currently, the number of inter-FPGA signals is considered as a substantial problem in NoC implemented on Multi-FPGA architectures. In this paper, we propose the integration…
Efficient MLP Digital Implementation on FPGA
2005
The efficiency and the accuracy of a digital feed-forward neural networks must be optimized to obtain both high classification rate and minimum area on chip. In this paper an efficient MLP digital implementation. The key features of the hardware implementation are the virtual neuron based architecture and the use of the sinusoidal activation function for the hidden layer. The effectiveness of the proposed solutions has been evaluated developing different FPGA based neural prototypes for the High Energy Physics domain and the automatic Road Sign Recognition domain. The use of the sinusoidal activation function decreases hardware resource employment of about 32% when compared with the standar…
A Dual-Core Coprocessor with Native 4D Clifford Algebra Support
2012
Geometric or Clifford Algebra (CA) is a powerful mathematical tool that is attracting a growing attention in many research fields such as computer graphics, computer vision, robotics and medical imaging for its natural and intuitive way to represent geometric objects and their transformations. This paper introduces the architecture of CliffordCoreDuo, an embedded dual-core coprocessor that offers direct hardware support to four-dimensional (4D) Clifford algebra operations. A prototype implementation on an FPGA board is detailed. Experimental results show a 1.6× average speedup of CliffordCoreDuo in comparison with the baseline mono-core architecture. A potential cycle speedup of about 40× o…