6533b7ddfe1ef96bd1274b4c
RESEARCH PRODUCT
A Hardware and Secure Pseudorandom Generator for Constrained Devices
Luigi MarangioMohammed BakiriStefano GalatoloJean-françois CouchotChristophe Guyeuxsubject
Applied cryptography; Chaotic circuits; Constrained devices; Discrete dynamical systems; FPGA; Lightweight Cryptography; Random number generators; Statistical tests; Control and Systems Engineering; Information Systems; Computer Science Applications1707 Computer Vision and Pattern Recognition; Electrical and Electronic EngineeringHardware security moduleComputer scienceRandom number generationCryptography[INFO.INFO-SE]Computer Science [cs]/Software Engineering [cs.SE]02 engineering and technologyPseudorandom generatorConstrained devicesLightweight CryptographyChaotic circuits[INFO.INFO-IU]Computer Science [cs]/Ubiquitous Computing[INFO.INFO-CR]Computer Science [cs]/Cryptography and Security [cs.CR]PermutationRandom number generatorsStatistical tests0202 electrical engineering electronic engineering information engineeringElectrical and Electronic EngineeringField-programmable gate arrayThroughput (business)FPGAPseudorandom number generatorGenerator (category theory)business.industry020208 electrical & electronic engineeringComputer Science Applications1707 Computer Vision and Pattern Recognition020206 networking & telecommunicationsDiscrete dynamical systems[INFO.INFO-MO]Computer Science [cs]/Modeling and SimulationComputer Science ApplicationsApplied cryptography[INFO.INFO-MA]Computer Science [cs]/Multiagent Systems [cs.MA]Control and Systems EngineeringKey (cryptography)[INFO.INFO-ET]Computer Science [cs]/Emerging Technologies [cs.ET][INFO.INFO-DC]Computer Science [cs]/Distributed Parallel and Cluster Computing [cs.DC]businessComputer hardwareInformation Systemsdescription
Hardware security for an Internet of Things or cyber physical system drives the need for ubiquitous cryptography to different sensing infrastructures in these fields. In particular, generating strong cryptographic keys on such resource-constrained device depends on a lightweight and cryptographically secure random number generator. In this research work, we have introduced a new hardware chaos-based pseudorandom number generator, which is mainly based on the deletion of an Hamilton cycle within the $N$ -cube (or on the vectorial negation), plus one single permutation. We have rigorously proven the chaotic behavior and cryptographically secure property of the whole proposal: the mid-term effects of a slight modification of the seed (proven to be sensitive to the initial conditions) or of the inputted generator cannot be predicted. The proposal has been fully deployed on a FPGA and 65 $\text{nm}$ ASIC, it runs completely in parallel while consuming as low resources as possible, and achieving: (a) 11.5 Gb/s for FPGA and 9.4 Gb/s for ASIC random bit throughput, (b) $3.3\,\mu \text{W}$ (LF) to $7.8 \,\text{mW}$ (UHF) total power consumption with $5\%$ leakage power, measured at $1.32\,\text{V}$ , and (c) able to successfully pass the statistical tests of NIST and TestU01 (BigCrush).
| year | journal | country | edition | language |
|---|---|---|---|---|
| 2018-08-01 | IEEE Transactions on Industrial Informatics |