Search results for "programma"

Обозрѣніе преподаванія по предмету государственнаго устройства Россіи и главнѣйшихъ державъ

1912

VALUTAZIONE DELLE PERFORMANCE E ATTIVITÀ DI INDIRIZZO, MONITORAGGIO E CONTROLLO SULLA PROGRAMMAZIONE PUBBLICA REGIONALE DEI FONDI STRUTTURALI. APPROC…

2014

La programmazione pubblica regionale attraversa un momento di forte criticità interna legata al soggetto attuatore regionale, caratterizzata da una lentissima attuazione dei programmi operativi cofinanziati dalla Commissione Europea. In risposta alle emergenze economiche e sociali, l’amministrazione regionale necessita di strumenti in grado di comunicare efficacemente azioni e risultati che possono positivamente influenzare la vita sociale e civile della comunità regionale. In particolare, gli operatori economici e, in generale, tutti i portatori di interesse, basano i propri atteggiamenti e le proprie scelte sulle aspettative delle dinamiche attese nei settori economici e sociali in cui op…

Development of a Fractional PI controller in an FPGA environment for a Robust High-Performance PMSM Electrical Drive

2021

This paper proposes the application of a Fractional Order PI (FOPI) in the speed loop of a high performance PMSM drive to obtain both speed tracking and load rejection performance with a 1-DOF Proportional Integral (PI) controller and 2-DOF Integral Proportional (IP) controller. Hardware validation was implemented in Field Programmable Gate Array on the LabVIEW environment, based on the National Instruments System-on-Module sbRIO-9651 with Xilinx Zynq-7020. Simulation and experimental results are presented to comparing the performance of a PI, IP and FOPI controllers in the speed loop of a Field Oriented Control (FOC) of a Permanent Magnet Synchronous Motor (PMSM).

Distributed Leader Election and Computation of Local Identifiers for Programmable Matter

2019

International audience; The context of this paper is programmable matter, which consists of a set of computational elements, called particles, in an infinite graph. The considered infinite graphs are the square, triangular and king grids. Each particle occupies one vertex, can communicate with the adjacent particles, has the same clockwise direction and knows the local positions of neighborhood particles. Under these assumptions, we describe a new leader election algorithm affecting a variable to the particles, called the k-local identifier, in such a way that particles at close distance have each a different k-local identifier. For all the presented algorithms, the particles only need a O(…

Fault Emulation for Dependability Evaluation of VLSI Systems

2008

Advances in semiconductor technologies are greatly increasing the likelihood of fault occurrence in deep-submicrometer manufactured VLSI systems. The dependability assessment of VLSI critical systems is a hot topic that requires further research. Field-programmable gate arrays (FPGAs) have been recently pro posed as a means for speeding-up the fault injection process in VLSI systems models (fault emulation) and for reducing the cost of fixing any error due to their applicability in the first steps of the development cycle. However, only a reduced set of fault models, mainly stuck-at and bit-flip, have been considered in fault emulation approaches. This paper describes the procedures to inje…

CIPRNG: A VLSI Family of Chaotic Iterations Post-Processings for $\mathbb {F}_{2}$ -Linear Pseudorandom Number Generation Based on Zynq MPSoC

2018

Hardware pseudorandom number generators are continuously improved to satisfy both physical and ubiquitous computing security system challenges. The main contribution of this paper is to propose two post-processing modules in hardware, to improve the randomness of linear PRNGs while succeeding in passing the TestU01 statistical battery of tests. They are based on chaotic iterations and are denoted by CIPRNG-MC and CIPRNG-XOR. They have various interesting properties, encompassing the ability to improve the statistical profile of the generators on which they iterate. Such post-processing have been implemented on FPGA and ASIC without inferring any blocs (RAM or DSP). A comparison in terms of …

Optimized FPGA-implementation of quadrature DDS

2003

This paper presents the optimized implementation of high performance quadrature direct digital synthesizers (DDS). Although VLSI designs and optimizations have already been discussed in the literature they may not be successfully translated into an FPGA-based technology. This work examines each phase-to-amplitude mapping technique, such as ROM compression and partitioning techniques and the CORDIC algorithm, and it proposes the most suitable structure for Virtex FPGAs in order to obtain the most efficient implementation in terms of area and throughput.

Vietējo pašvaldību problēmas zilo pludmaļu piesārņojošo atkritumu situācijas uzlabošanā

2019

Jūras piesārņojošo atkritumu (JPA) galvenais cēlonis ir cilvēka saimnieciskas vai nesaimnieciskas darbības sekas. Lai mazinātu atkritumu nonākšanu pasaules okeānā, sabiedrības ieradumus, attiecībā uz atkritumiem, ir nepieciešams mainīt uz aprites ekonomikas balstītiem pamaprincipiem. Lai piemērotu efektīvas rīcības JPA samazināšanai, būtiski ir aptvert JPA avotus, cēloņus, ietekmes un tendences nākotnē. Bakalaura darba mērķis ir apzināt pašvaldībām iespējamos JPA rašanās riskus un avotus, iegūtos rezultātus analizēt, lai piemērotu efektīvas rīcības, kas mazina draudus atkritumiem rasties un nonākt jūrās. Lai gan Zilā karoga pašvaldībām jau ir labas vides pārvaldības risinājumi, tomēr kampaņ…

An Embedded Real-Time Lane-Keeper for Automatic Vehicle Driving

2008

Automatic vehicle driving involves several issues, such as the capability to follow the road and keep the right lane, to maintain the distance between vehicles, to regulate vehiclepsilas speed, to find the shortest route to a destination. In this paper a real-time automatic lane-keeper is proposed. The main features of the system are the lane markers location process as well as the computation of the vehiclepsilas steering lock. The above techniques require high elaboration speed to execute, check and complete an operation before a prearranged time. Clearly if system processing exceeds the deadline, the whole operation became meaningless or, in the meantime, the vehicle can reach a critical…

Global Trigger Technological Demonstrator for ATLAS Phase-II upgrade

2020

ATLAS detector at the LHC will undergo a major Phase-II upgrade for the High Luminosity LHC. The upgrade affects all major ATLAS systems, including the Trigger and Data Acquisition systems. As part of the Level-0 Trigger System, the Global Trigger uses full-granularity calorimeter cells to perform algorithms, refines the trigger objects and applies topological requirements. The Global Trigger uses a Global Common Module as the building block of its design. To achieve a high input and output bandwidth and substantial processing power, the Global Common Module will host the most advanced FPGAs and optical modules. In order to evaluate the new generation of optical modules and FPGAs running at…