0000000000008986
AUTHOR
G. Ammendola
Reliability and Retention Study of Nanocrystal Cell Array
We have studied nanocrystal memory arrays with 2.56 × 105 cells (256kb) in which Si nanocrystals have been obtained by CVD deposition on a 4nm tunnel oxide. The cells in the array are programmed and erased by electron tunneling through the SiO2 dielectric. We find that the threshold voltage distribution has little spread. In addition the arrays are also very robust with respect to drain stress and show good retention.
Nanocrystal metal-oxide-semiconductor memories obtained by chemical vapor deposition of Si nanocrystals
We have realized nanocrystal memories by using silicon quantum dots embedded in silicon dioxide. The Si dots with the size of few nanometers have been obtained by chemical vapor deposition on very thin tunnel oxides and subsequently coated with a deposited SiO2 control dielectric. A range of temperatures in which we can adequately control a nucleation process, that gives rise to nanocrystal densities of ∼3×1011 cm−2 with good uniformity on the wafer, has been defined. The memory effects are observed in metal-oxide-semiconductor capacitors or field effect transistors by significant and reversible flat band or threshold voltage shifts between written and erased states that can be achieved by …
Nanocrystal memories for FLASH device applications
Nanocrystals memory cells, in which the conventional polysilicon floating gate is replaced by an array of silicon nanocrystals, have been fabricated and characterized. Single cells and cell arrays of 1 Mb and 10 k have been realized by using a conventional 0.15 μm FLASH technology. Si nanocrystals are deposited on top of tunnel oxide by chemical vapor deposition. Properties of the memory cell have been investigated both for NAND and NOR applications in terms of program/erase window and programming times. Suitable program/erase threshold voltage window can be achieved with fast voltage pulses by adequate choice of tunnel and control dielectric. The feasibility of dual bit storage is also pro…
Peculiar aspects of nanocrystal memory cells: Data and extrapolations
Nanocrystal memory cell are a promising candidate for the scaling of nonvolatile memories in which the conventional floating gate is replaced by an array of nanocrystals. The aim of this paper is to present the results of a thorough investigation of the possibilities and the limitations of such new memory cell. In particular, we focus on devices characterized by a very thin tunnel oxide layer and by silicon nanocrystals formed by chemical vapor deposition. The direct tunneling of the electrons through the tunnel oxide, their storage into the silicon nanocrystals, and furthermore, retention, endurance, and drain turn-on effects, well-known issues for nonvolatile memories, are all investigate…
Adherence issues related to sublingual immunotherapy as perceived by allergists.
Silvia Scurati1, Franco Frati1, Gianni Passalacqua2, Paola Puccinelli1, Cecile Hilaire1, Cristoforo Incorvaia3, Italian Study Group on SLIT Compliance 1Scientific and Medical Department, Stallergenes, Milan, Italy; 2Allergy and Respiratory Diseases, Department of Internal Medicine, Genoa; 3Allergy/Pulmonary Rehabilitation, ICP Hospital, Milan, ItalyObjectives: Sublingual immunotherapy (SLIT) is a viable alternative to subcutaneous immunotherapy to treat allergic rhinitis and asthma, and is widely used in clinical practice in many European countries. The clinical efficacy of SLIT has been established in a number of clinical trials and meta-analyses. However, because SLIT is self-administered…
Multi-bit storage through Si nanocrystals embedded in SiO2
We have realized Si nanocrystal memory cells in which the Si dots have been deposited by CVD on SiO2 and then covered by a CVD control oxide. In this paper, we report a study on the potential of these cells for dual bit storage. © 2004 Elsevier B.V. All rights reserved.
Memory effects in MOS devices based on Si quantum dots
Silicon quantum dots have been deposited on top of a 3-nm tunnel oxide by Low Pressure Chemical Vapour Deposition (LPCVD) and coated with a 7-nm Chemical Vapour Deposited (CVD) oxide. This stack was then incorporated in Metal-Oxide-Semiconductor structure and used as floating gate of a memory cell. The presence of 3 nm of tunnel oxides allows the injection of the charge by direct tunnel (DT) using low voltages for both program and erase operations. The charge stored in the quantum dots is able to produce a well-detectable flat band shift in the capacitors or, equivalently, a threshold voltage shift in the transistors. Furthermore, due to the presence of SiO 2 between the grains, the lateral…
How far will Silicon nanocrystals push the scaling limits of NVMs technologies?
For the first time, memory devices with optimized high density (2E12#/cm/sup 2/) LPCVD Si nanocrystals have been reproducibly achieved and studied on an extensive statistical basis (from single cell up to 1 Mb test-array) under different programming conditions. An original experimental and theoretical analysis of the threshold voltage shift distribution shows that Si nanocrystals have serious potential to push the scaling of NOR and NAND flash at least to the 35 nm and 65 nm nodes, respectively.
Memory effects in single-electron nanostructures
We investigate the memory function at room temperature in devices based on quantum dots. By Low Pressure Chemical Vapour Deposition (LPCVD) we deposited Si dots embedded in SiO2. On these devices flat band voltage shifts were well detected at low write voltages for write times of the order of milliseconds, and furthermore, a plateau in the flat band voltage shift, maybe consequence of Coulomb blockdale, was observed.
Localized charge storage in nanocrystal memories: Feasibility of a multi-bit cell
We have realized Si nanocrystal memory cells in which the Si dots have been deposited by chemical vapor deposition (CVD) on the tunnel oxide and then covered by a CVD control oxide. In this paper we report a study on the potential of this type of cells for multi-bit storage. In particular, the possibilities offered by these devices from the point of view of program/erase mechanisms, endurance, and charge retention are shown and discussed.
Programming options for nanocrystal MOS memories
Nanocrystal memories represent a promising candidate for the scaling of FLASH memories. In these devices, the charge is not stored in a continuous floating gate but in a discontinuous layer composed by numerous discrete silicon quantum dots well separated one from the other.The nanocrystals of radius of few nanometers are realized by chemical vapor deposition (CVD) of silicon on the tunnel oxide of 2.8 nm of thickness. These islands have been coated with a control oxide of 7 nm formed by CVD and incorporated in Metal-Oxide-Semiconductor structure. The devices are programmed and erased by tunnelling using low voltages and fast times. In addition, the programming can be easily achieved also b…
Nanocrystal MOS memories obtained by LPCVD deposition of Si nanograins
We have realized silicon quantum dots embedded in SiO2 which act as nano-floating gates of MOS memories. The dots with nanometer sizes have been deposited by LPCVD on a 3nm tunnel oxide. Two processes at a fixed pressure have been explored by varying the temperature. SiH4 with a N2 carrier gas have been used in the former case, SiH4 and H2 have been used in the latter. In both cases a nanocrystalline silicon layer is obtained, with nanocrystals a density higher than 1011 cm-2. The process with H2 carrier gas is more controllable and leads to the formation of nanocrystals with a more regular shape. In both cases the density of grains is able to originate detectable threshold shifts in the me…