0000000001294283
AUTHOR
Kamel Messaoudi
Hardware/Software Implementation of Image Processing Systems Based on ARM Processor
International audience; In this paper we present a hardware/software platform for real-time image processing. We start with the creation of the hardware part based on the ARM processor (PS) with various drivers (PL) for reading, recording and displaying images. Using the SDK tool (Software Development Kit), we add software parts for the realization of some basic image processing algorithms. We use the Xilinx-VIVADO2016 tool for the proposed system design and we use the rapid development board (Xilinx-ZedBoard) for practical implementations. To realize the principle of codesign, we add hardware IPs (RTL level) for the implementation of the same image processing algorithms. To avoid the detai…
Implementation of Universal Digital Architecture using 3D-NoC for Mobile Terminal
International Conference on Control, Decision and Information Technologies (CoDIT), Ecole Natl Ingenieurs Metz, Metz, FRANCE, NOV 03-05, 2014; International audience; The need to integrate multiple wireless communication protocols into a single low-cost flexible hardware platform is prompted by the increasing number of emerging communication protocols and applications in modern embedded systems. So the current challenge is to design of new digital architectures, in addition to its ability to take over of many functions. In this paper we have identified similarities between the despreader units in Rake receiver and the processor element in FFT-SDF (Fast Fourier Transform-Single path Delay Fe…
Adaptive Hardware Implementation for the Deblocking Filter Used in H.264/AVC Using System GeneratorEnter title
International audience; Xilinx System Generator is a Matlab/Simulink high-level based design tool especially for the development of complex digital circuits using Hardware Description Language (HDL). In this paper we propose a high level model for the deblocking filter used in H.264/AVC using System Generator of Matlab/Simulink. Synthesis results are compared with implementations realized using RTL level. The proposed model allows for rapid edits of the architectures and permits the implementation of filters used in other standards and norms (HEVC for example). The proposed implementations are verified using Xilinx-Virtex5 platforms.
A Novel Approach for Accelerating Bitstream Relocation in Many-core Partially Reconfigurable Applications
International audience; Partial Bitstream Relocation (PBR) has been introduced in recent years, as a means to overcome the limitations of the traditional Xilinx Partial Reconfiguration flow, particularly in terms of the limited module placement, a fact that can greatly reduce the memory footprint of applications which require multiple implementations of the same module... However, PBR consumes scarce resources in hardware implementations, and introduces a prohibitive time overhead when done in software. This is particularly true in applications such as large scalable systems, which typically require multiple copies of the same module to accelerate a task, but in which the relocation time ov…
A novel methodology for accelerating bitstream relocation in partially reconfigurable systems
International audience; Xilinx Virtex FPGAs offer the possibility of Partial Reconfiguration (PR). Arbitrary tasks can be allocated and de-allocated onto FPGA without system interruption. However, mapping a task to any available PR region requires a unique partial bitstream for each partition, hence reducing memory storage requirements. In recent years, an interest on overcoming this problem has lead to the concept of Partial Bitstream Relocation (PBR). The principle is to perform bitstream modification to map it to different regions. However, PBR consumes scarce resources in hardware implementations, and introduces a prohibitive time overhead when done in software. In order to find the bes…
High Level Modeling and Hardware Implementation of Image Processing Algorithms Using XSG
International audience; Design of Systems-on-Chip has become very common especially with the remarkable advances in the field of high-level system modeling. In recent years, Matlab also offers a Simulink interface for the design of hardware systems. From a high-level specification, Matlab provides self-generation of HDL codes and/or FPGA configuration codes while providing other benefits of easy simulation. In addition, a large part of the Systems-on-Chip use at least one image processing algorithm and at the same time border detection is one of the most used algorithms. This paper presents a study and a hardware implementation of various algorithms of borders detection realized under Xilin…
A Spatial Pyramidal Decomposition Method for ear representation using local dual cross patterns
International audience; In recent years, several scientific works are oriented to develop optimal ear representation, for ear recognition, which is discriminant, compact, and easyto-implement to ensure the best performance in terms of accuracy, computation cost, and storage requirement. In this manner, this paper presents a novel ear representation based on texture analysis framework, which relies mainly on Dual Cross Pattern (DCP) descriptor and Spatial Pyramid Histogram (SPH) method. The features are extracted using DCP descriptor to capture the textural structure then, the SPH of horizontal ear decomposition is applied to obtain the local information. The feature vector representations o…