6533b82efe1ef96bd12931fe
RESEARCH PRODUCT
SEGR in SiO${}_2$–Si$_3$N$_4$ Stacks
Michele MuschitielloFrancesco PintacudaMarty R. ShaneyfeltAri VirtanenMikko RossiArto JavanainenJames R. SchwankVeronique Ferlet-cavroisHeikki KettunenJukka JaatinenAlexandre Louis Bossersubject
PhysicsNuclear and High Energy Physicsta114Condensed matter physicsbusiness.industrymodelingDielectricMOSGate voltageSingle Event Gate Rupture (SEGR)Nuclear Energy and EngineeringOptoelectronicsElectrical and Electronic Engineeringbusinesssemi-empiricalDeposition (law)description
Abstract. This work presents experimental Single Event Gate Rupture (SEGR) data for Metal–Insulator–Semiconductor (MIS) devices, where the gate dielectrics are made of stacked SiO2–Si3N4 structures. A semi-empirical model for predicting the critical gate voltage in these structures under heavy-ion exposure is first proposed. Then interrelationship between SEGR cross- section and heavy-ion induced energy deposition probability in thin dielectric layers is discussed. Qualitative connection between the energy deposition in the dielectric and the SEGR is proposed. peerReviewed
| year | journal | country | edition | language |
|---|---|---|---|---|
| 2014-08-01 | IEEE Transactions on Nuclear Science |