Semi-Empirical Model for SEGR Prediction

2013

The underlying physical mechanisms in single event gate rupture (SEGR) are not known precisely. SEGR is expected to occur when the energy deposition due to a heavy ion strike exceeds a certain threshold simultaneously with sufficient electric field across the gate dielectric. Typically the energy deposition is described by using the linear energy transfer (LET) of the given ion. Previously the LET has been demonstrated not to describe the SEGR sufficiently. The work presented here introduces a semi-empirical model for the SEGR prediction based on statistical variations in the energy deposition which are described theoretically.

SEGR in SiO<inf>2</inf>-Si<inf>3</inf>N<inf>4</inf> stacks

2013

SEGR in SiO${}_2$–Si$_3$N$_4$ Stacks

2014

Abstract. This work presents experimental Single Event Gate Rupture (SEGR) data for Metal–Insulator–Semiconductor (MIS) devices, where the gate dielectrics are made of stacked SiO2–Si3N4 structures. A semi-empirical model for predicting the critical gate voltage in these structures under heavy-ion exposure is first proposed. Then interrelationship between SEGR cross- section and heavy-ion induced energy deposition probability in thin dielectric layers is discussed. Qualitative connection between the energy deposition in the dielectric and the SEGR is proposed. peerReviewed

Influence of beam conditions and energy for SEE testing

2012

GANIL/Applications industrielles; The effects of heavy-ion test conditions and beam energy on device response are investigated. These effects are illustrated with two types of test vehicles: SRAMs and power MOSFETs. In addition, GEANT4 simulations have also been performed to better understand the results. Testing to high fluence levels is required to detect rare events. This increases the probability of nuclear interactions. This is typically the case for power MOSFETs, which are tested at high fluences for single event burnout or gate rupture detection, and for single-event-upset (SEU) measurement in SRAMs below the direct ionization threshold. Differences between various test conditions (…