6533b838fe1ef96bd12a4630

RESEARCH PRODUCT

Progress towards innovative and energy efficient logic circuits

Giovanni Piero PepeGaetano SalinaAntonino MessinaGiovanni CarapellaCarlo BaroneMikkel EjrnaesAngela NigroLoredana ParlatoMikhail LisitskiyMatteo CirilloAnna NapoliFabrizio BobbaCarmine AttanasioSergio PaganoNadia MartuccielloV. MerloAntonio LeoMassimiliano LucciBenedetto MilitelloRoberto Cristiano

subject

Josephson effectHistoryJosephson junctionsComputer scienceNanowireHardware_PERFORMANCEANDRELIABILITYInductorSQUIDEducationlaw.inventionlawCondensed Matter::SuperconductivityHardware_INTEGRATEDCIRCUITSElectronic circuitHardware_MEMORYSTRUCTURESSettore FIS/03business.industryLogic familyElectrical engineeringSuperconductive nanowire logic memoriesComputer Science ApplicationsLogic gateState (computer science)ResistorbusinessSuperconductive nanowire logic memories; Josephson junctions; SQUIDHardware_LOGICDESIGN

description

Abstract The integration of superconductive nanowire logic memories and energy efficient computing Josephson logic is explored. Nanowire memories are based on the integration of switchable superconducting nanowires with a suitable magnetic material. These memories exploit the electro-thermal operation of the nanowires to efficiently store and read a magnetic state. In order to achieve proper memory operation a careful design of the nanowire assembly is necessary, as well as a proper choice of the magnetic material to be employed. At present several new superconducting logic families have been proposed, all tending to minimize the effect of losses in the digital Josephson circuits replacing resistors by adequate combinations of inductors in the logic gates. Among those, the nSQUID concept relies on the propagation of vortices along underdamped Josephson transmission lines. While, in principle, this logic family provides very low dissipation, several issues, such as speed and stability, have yet to be addressed. The current status of design and testing of n-SQUID logic gates and circuits as well as of the design and implementation of the nanowire memories is reported

10.1088/1742-6596/1559/1/012009http://hdl.handle.net/2108/250774