Search results for "CIRCUIT"
showing 10 items of 936 documents
Non-linear neuro-inspired circuits and systems: Processing and learning issues
2018
In this chapter the main elements useful for the design and realization of the neural architectures reported in the following chapters will be presented. Considering spiking and non-spiking neurons, the models used for implementing each of them, the synaptic models, the basic learning and plasticity algorithms and the network architectures will be introduced and analysed. The key elements that led to their selection and application in the developed neuro-inspired systems will be discussed briefly.
Fault-Tolerant Application Mapping on to ZMesh topology based Network-on-Chip Design
2020
This paper proposes Particle Swarm Optimization (PSO) based fault-tolerant application mapping on to ZMesh topology based Network-on-Chip (NoC) design. Permanent faults in application cores has been considered and performed application mapping using PSO. The major contribution of this paper is to find out the best position for the spare core to be placed in the network using PSO. Experimentations have been carried out by scaling the ZMesh network size and percentage of network faults. The results show that the proposed approach leads to minimum overhead in communication cost over fault-free result.
Active snubber network design and implementation on the primary side of an isolated Ćuk converter realizing soft-switching for efficiency …
2008
This paper describes the process of improving the efficiency of an existing isolated DC/DC converter based on CUK topology with secondary side synchronous rectification, by means of the introduction of an active snubber network on the primary side. The snubber circuit reduces to zero the switching losses during the off-time interval of secondary SR. In particular, the efficiency improvement is due to the elimination of the primary MOSFET Coss output capacitance losses, and mainly of the reverse recovery losses on the secondary SR MOSFET. However, the insertion of the active snubber creates itself additional losses in the circuit, and therefore to measure the really introduced benefit it is …
Designing Frame Relay WAN Networks with Trade-Off between Link Cost and Performance
2014
This paper is focused on the problem of designing a Wide Area Network topology with trade-off between link cost and response time to users. The L2 technology chosen for the research is a Frame Relay based solution. The link capacities in the network and the routes used by packets are determined in a way to minimize network cost and response time at the same time. In FR networks link capacity corresponds directly to CIR parameter which makes the presented numerical results very useful in practice, especially during preliminary network design in the Design Phase of the PPDIOO methodology.
Editorial: Neuromodulatory ascending systems: Their influence at the microscopic and macroscopic levels
2022
Brain activity and behavior are constantly changing (Puig et al., 2014; Disney, 2021). Recent studies in both animal models and humans have revealed that such variations are not random in nature but controlled through slow-acting neuromodulatory systems...
Transient cortical circuits match spontaneous and sensory-driven activity during development.
2020
At the earliest developmental stages, spontaneous activity synchronizes local and large-scale cortical networks. These networks form the functional template for the establishment of global thalamocortical networks and cortical architecture. The earliest connections are established autonomously. However, activity from the sensory periphery reshapes these circuits as soon as afferents reach the cortex. The early-generated, largely transient neurons of the subplate play a key role in integrating spontaneous and sensory-driven activity. Early pathological conditions—such as hypoxia, inflammation, or exposure to pharmacological compounds—alter spontaneous activity patterns, which subsequently in…
Neurohybrid Memristive CMOS-Integrated Systems for Biosensors and Neuroprosthetics
2020
Here we provide a perspective concept of neurohybrid memristive chip based on the combination of living neural networks cultivated in microfluidic/microelectrode system, metal-oxide memristive devices or arrays integrated with mixed-signal CMOS layer to control the analog memristive circuits, process the decoded information, and arrange a feedback stimulation of biological culture as parts of a bidirectional neurointerface. Our main focus is on the state-of-the-art approaches for cultivation and spatial ordering of the network of dissociated hippocampal neuron cells, fabrication of a large-scale cross-bar array of memristive devices tailored using device engineering, resistive state program…
Technology Impact on Neutron-Induced Effects in SDRAMs : A Comparative Study
2021
International audience; This study analyses the response of synchronous dynamic random access memories to neutron irradiation. Three different generations of the same device with different node sizes (63, 72, and 110 nm) were characterized under an atmospheric-like neutron spectrum at the ChipIr beamline in the Rutherford Appleton Laboratories, UK. The memories were tested with a reduced refresh rate to expose more single-event upsets and under similar conditions provided by a board specifically developed for this type of study in test facilities. The board has also been designed to be used as a nanosatellite payload in order to perform similar tests. The neutron-induced failures were studi…
A Method for Accurate Measurements of Optimum Noise Parameters of Microwave Transistors
1985
A method for measuring losses of the tuner network used as noise source admittance transformer in transistor noise parameter test-set is presented. Since the method is based on noise figure measurements, tuner losses can be determined on-line while performing measurements for determining transistor noise parameters. As experimental verifications the optimum noise parameters of a GaAs FET in the 4 - 12 GHz frequency range, measured through a computer-assisted measuring system, are reported.
ACCURATE MEASUREMENTS OF OPTIMUM NOISE PARAMETERS OF MICROWAVE TRANSISTORS
1986
A method for measuring losses of the tuner network used as noise source admittance transformer in transistor noise parameter test-set is presented. Since the method is based on noise figure measurements, tuner losses can be determined on-line while performing measurements for determining transistor noise parameters. As experimental verifications the optimum noise parameters of a GaAs FET in the 4 - 12 GHz frequency range, measured through a computer-assisted measuring system, are reported.