Search results for "CSTR"
showing 10 items of 45 documents
On the Quantum and Classical Complexity of Solving Subtraction Games
2019
We study algorithms for solving Subtraction games, which are sometimes referred as one-heap Nim games.
Efficient FPGA Implementation of an Adaptive Noise Canceller
2006
A hardware implementation of an adaptive noise canceller (ANC) is presented. It has been synthesized within an FPGA, using a modified version of the least mean square (LMS) error algorithm. The results obtained so far show a significant decrease of the required gate count when compared with a standard LMS implementation, while increasing the ANC bandwidth and signal to noise (S/N) ratio. This novel adaptive noise canceller is then useful for enhancing the S/N ratio of data collected from sensors (or sensor arrays) working in noisy environment, or dealing with potentially weak signals.
The promise of spintronics for unconventional computing
2021
Novel computational paradigms may provide the blueprint to help solving the time and energy limitations that we face with our modern computers, and provide solutions to complex problems more efficiently (with reduced time, power consumption and/or less device footprint) than is currently possible with standard approaches. Spintronics offers a promising basis for the development of efficient devices and unconventional operations for at least three main reasons: (i) the low-power requirements of spin-based devices, i.e., requiring no standby power for operation and the possibility to write information with small dynamic energy dissipation, (ii) the strong nonlinearity, time nonlocality, and/o…
Application based on dynamic reconfiguration of field-programmable gate arrays: JPEG 2000 arithmetic decoder
2005
This paper describes the implementation of a part of the JPEG 2000 algorithm (MQ decoder and arithmetic decoder) on a field-programmable gate array (FPGA) board by using dynamic reconfiguration. A comparison between static and dynamic reconfiguration is presented, and new analysis criteria (spatiotemporal efficiency, logic cost, and performance time) have been defined. The MQ decoder and arithmetic decoder are attractive for dynamic reconfiguration implementation in applications without parallel processing. This implementation is done on an architecture designed to study the dynamic reconfiguration of FPGAs: the ARDOISE architecture. The obtained implementation, based on four partial config…
Some remarks on unconditionally convergent multipliers
2017
We present some results concerning the representation of unconditionally convergent multipliers, including a reformulation of a conjecture of Balazs and Stoeva.
Pairwise DNA Sequence Alignment Optimization
2015
This chapter presents a parallel implementation of the Smith-Waterman algorithm to accelerate the pairwise alignment of DNA sequences. This algorithm is especially computationally demanding for long DNA sequences. Parallelization approaches are examined in order to deeply explore the inherent parallelism within Intel Xeon Phi coprocessors. This chapter looks at exploiting instruction-level parallelism within 512-bit single instruction multiple data instructions (vectorization) as well as thread-level parallelism over the many cores (multithreading using OpenMP). Between coprocessors, device-level parallelism through the compute power of clusters including Intel Xeon Phi coprocessors using M…
A Note on Keys and Keystreams of Chacha20 for Multi-key Channels
2018
In this paper we analyze the keystreams generated by the Chacha20 stream cipher. We also compare these to the ones generated by its predecessor, the RC4 stream cipher. Due to the proposed multi-key channels in the upcoming TLS 1.3 standard we analyze the behavior of the keystream in the boundary case where there is a single bit difference between two keys used for the initiation of the stream cipher algorithms. The goal is to check whether a single bit change in the key has any predictable influence on the bits of the keystream output.
Versatile Direct and Transpose Matrix Multiplication with Chained Operations: An Optimized Architecture Using Circulant Matrices
2016
With growing demands in real-time control, classification or prediction, algorithms become more complex while low power and small size devices are required. Matrix multiplication (direct or transpose) is common for such computation algorithms. In numerous algorithms, it is also required to perform matrix multiplication repeatedly, where the result of a multiplication is further multiplied again. This work describes a versatile computation procedure and architecture: one of the matrices is stored in internal memory in its circulant form, then, a sequence of direct or transpose multiplications can be performed without timing penalty. The architecture proposes a RAM-ALU block for each matrix c…
Balls into non-uniform bins
2014
Balls-into-bins games for uniform bins are widely used to model randomized load balancing strategies. Recently, balls-into-bins games have been analysed under the assumption that the selection probabilities for bins are not uniformly distributed. These new models are motivated by properties of many peer-to-peer (P2P) networks, which are not able to perfectly balance the load over the bins. While previous evaluations try to find strategies for uniform bins under non-uniform bin selection probabilities, this paper investigates heterogeneous bins, where the "capacities" of the bins might differ significantly. We show that heterogeneous environments can even help to distribute the load more eve…
Polynomial method to study the entanglement of pure N-qubit states
2009
We present a mapping which associates pure N-qubit states with a polynomial. The roots of the polynomial characterize the state completely. Using the properties of the polynomial we construct a way to determine the separability and the number of unentangled qubits of pure N-qubit states.