Search results for "Circuits"

showing 10 items of 358 documents

Experimental study of low-voltage surge protection device response in realistic systems

2008

Experimental results on low-voltage surge protection under fast pulses in realistic wiring systems are presented. A fast voltage pulse generator is designed to provide fast voltage pulses with short steep fronts. The effective residual voltage of protected equipment is then investigated and compared with simulation results.

Engineeringbusiness.industrySurge arresterPulse generatorElectrical engineeringHardware_PERFORMANCEANDRELIABILITYCondensed Matter::Mesoscopic Systems and Quantum Hall EffectGenerator (circuit theory)Hardware_GENERALResidual voltageHardware_INTEGRATEDCIRCUITSElectronic engineeringVoltage pulseElectrical and Electronic EngineeringSurgebusinessLow voltageVoltageElectronics Letters
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Novel Fault-Tolerant Routing Technique for ZMesh Topology based Network-on-Chip Design

2020

This paper proposes a novel fault-tolerant routing technique for ZMesh topology based Network-on-Chip (NoC) design. The proposed algorithm caters the link faults and routes the data packets seamlessly to the destination. This algorithm has been compared with the existing techniques proposed for mesh topology counterparts. The experimentations have been carried out by increasing ZMesh network size and percentage of link faults. The results show that in the event of link failures the proposed algorithm routes the data from source to destination flawlessly.

Event (computing)Computer scienceNetwork packetMesh networking020206 networking & telecommunicationsFault toleranceTopology (electrical circuits)02 engineering and technologyLink (geometry)TopologyNetwork on a chip0202 electrical engineering electronic engineering information engineering020201 artificial intelligence & image processingRouting (electronic design automation)2020 15th IEEE Conference on Industrial Electronics and Applications (ICIEA)
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Hardware and firmware developments for the upgrade of the ATLAS Level-1 Central Trigger Processor

2014

The Central Trigger Processor (CTP) is the final stage of the ATLAS first level trigger system which reduces the collision rate of 40 MHz to a Level-1 event rate of 100 kHz. An upgrade of the CTP is currently underway to significantly increase the number of trigger inputs and trigger combinations, allowing additional flexibility for the trigger menu. We present the hardware and FPGA firmware of the newly designed core module (CTPCORE+) module of the CTP, as well as results from a system used for early firmware and software prototyping based on commercial FPGA evaluation boards. First test result from the CTPCORE+ module will also be shown.

Event (computing)business.industryComputer scienceFirmwareSoftware prototypingcomputer.software_genreUpgrademedicine.anatomical_structureTrigger concepts and systems (hardware and software)Atlas (anatomy)medicineLevel triggerDetectors and Experimental TechniquesField-programmable gate arraybusinessInstrumentationcomputerDigital electronic circuitsMathematical PhysicsComputer hardwareCollision rateJournal of Instrumentation
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Human experts vs. machines in taxa recognition

2020

The step of expert taxa recognition currently slows down the response time of many bioassessments. Shifting to quicker and cheaper state-of-the-art machine learning approaches is still met with expert scepticism towards the ability and logic of machines. In our study, we investigate both the differences in accuracy and in the identification logic of taxonomic experts and machines. We propose a systematic approach utilizing deep Convolutional Neural Nets with the transfer learning paradigm and extensively evaluate it over a multi-pose taxonomic dataset with hierarchical labels specifically created for this comparison. We also study the prediction accuracy on different ranks of taxonomic hier…

FOS: Computer and information sciencesComputer Science - Machine Learninghahmontunnistus (tietotekniikka)Computer scienceClassification approachTaxonomic expert02 engineering and technologyneuroverkotcomputer.software_genreConvolutional neural networkQuantitative Biology - Quantitative MethodsField (computer science)Machine Learning (cs.LG)Machine learning approachesStatistics - Machine LearningAutomated approachDeep neural networks0202 electrical engineering electronic engineering information engineeringTaxonomic rankQuantitative Methods (q-bio.QM)Classification (of information)Artificial neural networksystematiikka (biologia)Prediction accuracyIdentification (information)koneoppiminenMulti-image dataBenchmark (computing)020201 artificial intelligence & image processingConvolutional neural networksComputer Vision and Pattern RecognitionClassification errorsMachine Learning (stat.ML)Machine learningState of the artElectrical and Electronic EngineeringTaxonomySupport vector machinesLearning systemsbusiness.industryNode (networking)020206 networking & telecommunicationsComputer circuitsHierarchical classificationConvolutionSupport vector machineFOS: Biological sciencesTaxonomic hierarchySignal ProcessingBiomonitoringBenchmark datasetsArtificial intelligencebusinesscomputertaksonitSoftware
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Sparsity-Driven Digital Terrain Model Extraction

2020

We here introduce an automatic Digital Terrain Model (DTM) extraction method. The proposed sparsity-driven DTM extractor (SD-DTM) takes a high-resolution Digital Surface Model (DSM) as an input and constructs a high-resolution DTM using the variational framework. To obtain an accurate DTM, an iterative approach is proposed for the minimization of the target variational cost function. Accuracy of the SD-DTM is shown in a real-world DSM data set. We show the efficiency and effectiveness of the approach both visually and quantitatively via residual plots in illustrative terrain types.

FOS: Computer and information sciencesHardware_MEMORYSTRUCTURES010504 meteorology & atmospheric sciencesIterative methodComputer scienceComputer Vision and Pattern Recognition (cs.CV)0211 other engineering and technologiesComputer Science - Computer Vision and Pattern RecognitionTerrain02 engineering and technologyFunction (mathematics)Hardware_PERFORMANCEANDRELIABILITYComputerSystemsOrganization_PROCESSORARCHITECTURES01 natural sciencesData setHardware_INTEGRATEDCIRCUITSExtraction (military)Digital elevation modelAlgorithm021101 geological & geomatics engineering0105 earth and related environmental sciences
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Metastable memristive lines for signal transmission and information processing applications

2016

Traditional studies of memristive devices have mainly focused on their applications in nonvolatile information storage and information processing. Here, we demonstrate that the third fundamental component of information technologies-the transfer of information-can also be employed with memristive devices. For this purpose, we introduce a metastable memristive circuit. Combining metastable memristive circuits into a line, one obtains an architecture capable of transferring a signal edge from one space location to another. We emphasize that the suggested metastable memristive lines employ only resistive circuit components. Moreover, their networks (for example, Y-connected lines) have an info…

FOS: Computer and information sciencesResistive touchscreenTheoretical computer scienceCondensed Matter - Mesoscale and Nanoscale PhysicsComputer scienceInformation storageInformation processingComputer Science - Emerging TechnologiesFOS: Physical sciencesHardware_PERFORMANCEANDRELIABILITY02 engineering and technologySignal edge021001 nanoscience & nanotechnology01 natural sciencesLine (electrical engineering)Emerging Technologies (cs.ET)MetastabilityComponent (UML)Mesoscale and Nanoscale Physics (cond-mat.mes-hall)0103 physical sciencesHardware_INTEGRATEDCIRCUITSElectronic engineering010306 general physics0210 nano-technologyElectronic circuitPhysical Review E
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Lock-in range of PLL-based circuits with proportionally-integrating filter and sinusoidal phase detector characteristic

2016

In the present work PLL-based circuits with sinusoidal phase detector characteristic and active proportionally-integrating (PI) filter are considered. The notion of lock-in range -- an important characteristic of PLL-based circuits, which corresponds to the synchronization without cycle slipping, is studied. For the lock-in range a rigorous mathematical definition is discussed. Numerical and analytical estimates for the lock-in range are obtained.

FOS: MathematicsHardware_INTEGRATEDCIRCUITSDynamical Systems (math.DS)Mathematics - Dynamical Systems
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Label swapper device for spectral amplitude coded optical packet networks monolithically integrated on InP

2011

In this paper the design, fabrication and experimental characterization of an spectral amplitude coded (SAC) optical label swapper monolithically integrated on Indium Phosphide (InP) is presented. The device has a footprint of 4.8x1.5 mm 2 and is able to perform label swapping operations required in SAC at a speed of 155 Mbps. The device was manufactured in InP using a multiple purpose generic integration scheme. Compared to previous SAC label swapper demonstrations, using discrete component assembly, this label swapper chip operates two order of magnitudes faster. © 2011 Optical Society of America.

FabricationComputer sciencePacket networksPhosphinesIntegrationIndium phosphideIndiumSemiconductor laser theoryFootprint (electronics)chemistry.chemical_compoundDiscrete componentsSpectral amplitudeComputer Communication NetworksTEORIA DE LA SEÑAL Y COMUNICACIONESMonolithically integratedOptical labelsOptical amplifierSignal processingbusiness.industryExperimental characterizationInPOptical DevicesSignal Processing Computer-AssistedEquipment DesignChipIntegration schemeAtomic and Molecular Physics and OpticsOptical packet networksEquipment Failure Analysischemistryvisual_artElectronic componentvisual_art.visual_art_mediumIndium phosphideOptoelectronicsMonolithic integrated circuitsbusinessLabel swapping
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Giant Magnetoresistance (GMR) sensors for 0.35µm CMOS technology sub-mA current sensing

2014

This paper reports on the design and fabrication of microelectronic structures for non-invasive indirect electric current sensing at the IC level. A 0.35 ?m CMOS ASIC has been specifically developed for this purpose. Then, a low temperature post-process, fully compatible with the CMOS technology, has been applied for depositing Giant Magnetoresistive (GMR) sensors. Preliminary experimental results for obtaining the sensitivity of the devices are presented. The detection limit is estimated to be about 5 ?A.

FabricationMaterials scienceMagnetoresistancebusiness.industryElectrical engineeringGiant magnetoresistanceHardware_PERFORMANCEANDRELIABILITYIntegrated circuitlaw.inventionCMOSlawHardware_INTEGRATEDCIRCUITSOptoelectronicsMicroelectronicsElectric currentbusinessSensitivity (electronics)IEEE SENSORS 2014 Proceedings
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Multimodal and multicriteria analysis for VLSI expertises and defects localization

2017

The purpose of this manuscript is to exhibit the research work solving the issue of data processing stem from defect localization techniques. This step being decisive in the failure analysis process, scientists have to harness data coming from light emission and laser techniques. Nevertheless, this analysis process is sequential and only depends on the expert’s decision. This factor leads to a not quantified probability of localization. Consequently to solve these issues, a multimodal and multicriteria analysis has been developped, taking advantage of the heterogeneous andcomplementary nature of light emission and laser probing techniques. This kind of process is based on advanced level too…

Failure analysisdata fusionAnalyse de défaillancescircuits intégrés[SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronicsanalyse multimodale et multicritèrestraitement du signal/imagesignal/image processingVLSI[STAT] Statistics [stat]multimodal and criteria analysisdefect localizationlocalisation de défauts[PHYS.PHYS.PHYS-DATA-AN] Physics [physics]/Physics [physics]/Data Analysis Statistics and Probability [physics.data-an]fusion de données[SPI.SIGNAL] Engineering Sciences [physics]/Signal and Image processing
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