Search results for "Circuits"
showing 10 items of 358 documents
Programming options for nanocrystal MOS memories
2003
Nanocrystal memories represent a promising candidate for the scaling of FLASH memories. In these devices, the charge is not stored in a continuous floating gate but in a discontinuous layer composed by numerous discrete silicon quantum dots well separated one from the other.The nanocrystals of radius of few nanometers are realized by chemical vapor deposition (CVD) of silicon on the tunnel oxide of 2.8 nm of thickness. These islands have been coated with a control oxide of 7 nm formed by CVD and incorporated in Metal-Oxide-Semiconductor structure. The devices are programmed and erased by tunnelling using low voltages and fast times. In addition, the programming can be easily achieved also b…
Fault-Tolerant Application Mapping on to ZMesh topology based Network-on-Chip Design
2020
This paper proposes Particle Swarm Optimization (PSO) based fault-tolerant application mapping on to ZMesh topology based Network-on-Chip (NoC) design. Permanent faults in application cores has been considered and performed application mapping using PSO. The major contribution of this paper is to find out the best position for the spare core to be placed in the network using PSO. Experimentations have been carried out by scaling the ZMesh network size and percentage of network faults. The results show that the proposed approach leads to minimum overhead in communication cost over fault-free result.
Active snubber network design and implementation on the primary side of an isolated Ćuk converter realizing soft-switching for efficiency …
2008
This paper describes the process of improving the efficiency of an existing isolated DC/DC converter based on CUK topology with secondary side synchronous rectification, by means of the introduction of an active snubber network on the primary side. The snubber circuit reduces to zero the switching losses during the off-time interval of secondary SR. In particular, the efficiency improvement is due to the elimination of the primary MOSFET Coss output capacitance losses, and mainly of the reverse recovery losses on the secondary SR MOSFET. However, the insertion of the active snubber creates itself additional losses in the circuit, and therefore to measure the really introduced benefit it is …
Designing Frame Relay WAN Networks with Trade-Off between Link Cost and Performance
2014
This paper is focused on the problem of designing a Wide Area Network topology with trade-off between link cost and response time to users. The L2 technology chosen for the research is a Frame Relay based solution. The link capacities in the network and the routes used by packets are determined in a way to minimize network cost and response time at the same time. In FR networks link capacity corresponds directly to CIR parameter which makes the presented numerical results very useful in practice, especially during preliminary network design in the Design Phase of the PPDIOO methodology.
Editorial: Neuromodulatory ascending systems: Their influence at the microscopic and macroscopic levels
2022
Brain activity and behavior are constantly changing (Puig et al., 2014; Disney, 2021). Recent studies in both animal models and humans have revealed that such variations are not random in nature but controlled through slow-acting neuromodulatory systems...
Transient cortical circuits match spontaneous and sensory-driven activity during development.
2020
At the earliest developmental stages, spontaneous activity synchronizes local and large-scale cortical networks. These networks form the functional template for the establishment of global thalamocortical networks and cortical architecture. The earliest connections are established autonomously. However, activity from the sensory periphery reshapes these circuits as soon as afferents reach the cortex. The early-generated, largely transient neurons of the subplate play a key role in integrating spontaneous and sensory-driven activity. Early pathological conditions—such as hypoxia, inflammation, or exposure to pharmacological compounds—alter spontaneous activity patterns, which subsequently in…
Technology Impact on Neutron-Induced Effects in SDRAMs : A Comparative Study
2021
International audience; This study analyses the response of synchronous dynamic random access memories to neutron irradiation. Three different generations of the same device with different node sizes (63, 72, and 110 nm) were characterized under an atmospheric-like neutron spectrum at the ChipIr beamline in the Rutherford Appleton Laboratories, UK. The memories were tested with a reduced refresh rate to expose more single-event upsets and under similar conditions provided by a board specifically developed for this type of study in test facilities. The board has also been designed to be used as a nanosatellite payload in order to perform similar tests. The neutron-induced failures were studi…
A Method for Accurate Measurements of Optimum Noise Parameters of Microwave Transistors
1985
A method for measuring losses of the tuner network used as noise source admittance transformer in transistor noise parameter test-set is presented. Since the method is based on noise figure measurements, tuner losses can be determined on-line while performing measurements for determining transistor noise parameters. As experimental verifications the optimum noise parameters of a GaAs FET in the 4 - 12 GHz frequency range, measured through a computer-assisted measuring system, are reported.
ACCURATE MEASUREMENTS OF OPTIMUM NOISE PARAMETERS OF MICROWAVE TRANSISTORS
1986
A method for measuring losses of the tuner network used as noise source admittance transformer in transistor noise parameter test-set is presented. Since the method is based on noise figure measurements, tuner losses can be determined on-line while performing measurements for determining transistor noise parameters. As experimental verifications the optimum noise parameters of a GaAs FET in the 4 - 12 GHz frequency range, measured through a computer-assisted measuring system, are reported.
A Comparison of Special Bonding Techniques for Transmission and Distribution Cables under Normal and Fault Conditions
2021
In this article, a review of the existing special bonding techniques for medium voltage and high-voltage cables is presented. Special bonding techniques have the purpose of reducing sheath currents, thereby limiting copper losses and the reduction of the ampacity of cables. The literature review shows various bonding techniques and how these have evolved over the years thanks to new technologies. Simulations of each technique are performed in MATLAB/Simulink, to compare their strengths and drawbacks both under normal conditions and in the presence of a single-line-to-ground fault.