Search results for "Computer Science::Hardware Architecture"
showing 10 items of 67 documents
Domain-Knowledge Optimized Simulated Annealing for Network-on-Chip Application Mapping
2013
Network-on-Chip architectures are scalable on-chip interconnection networks. They replace the inefficient shared buses and are suitable for multicore and manycore systems. This paper presents an Optimized Simulated Annealing (OSA) algorithm for the Network-on-Chip application mapping problem. With OSA, the cores are implicitly and dynamically clustered using knowledge about communication demands. We show that OSA is a more feasible Simulated Annealing approach to NoC application mapping by comparing it with a general Simulated Annealing algorithm and a Branch and Bound algorithm, too. Using real applications we show that OSA is significantly faster than a general Simulated Annealing, withou…
Theory of Heterogeneous Circuits With Stochastic Memristive Devices
2022
We introduce an approach based on the Chapman-Kolmogorov equation to model heterogeneous stochastic circuits, namely, the circuits combining binary or multi-state stochastic memristive devices and continuum reactive components (capacitors and/or inductors). Such circuits are described in terms of occupation probabilities of memristive states that are functions of reactive variables. As an illustrative example, the series circuit of a binary memristor and capacitor is considered in detail. Some analytical solutions are found. Our work offers a novel analytical/numerical tool for modeling complex stochastic networks, which may find a broad range of applications.
Improving topological mapping on NoCs
2010
Networks-on-Chip (NoCs) have been proposed as an efficient solution to the complex communications on System-on-chip (SoCs). The design flow of network-on-chip (NoCs) include several key issues, and one of them is the decision of where cores have to be topologically mapped. This thesis proposes a new approach to the topological mapping strategy for NoCs. Concretely, we propose a new topological mapping technique for regular and irregular NoC platforms and its application for optimizing application specific NoC based on distributed and source routing.
A random-walk benchmark for single-electron circuits
2021
Mesoscopic integrated circuits aim for precise control over elementary quantum systems. However, as fidelities improve, the increasingly rare errors and component crosstalk pose a challenge for validating error models and quantifying accuracy of circuit performance. Here we propose and implement a circuit-level benchmark that models fidelity as a random walk of an error syndrome, detected by an accumulating probe. Additionally, contributions of correlated noise, induced environmentally or by memory, are revealed as limits of achievable fidelity by statistical consistency analysis of the full distribution of error counts. Applying this methodology to a high-fidelity implementation of on-dema…
Modeling and statistical characterization of wideband indoor radio propagation channels
2010
In this paper, we focus on the modeling of wideband single-input single-output (SISO) mobile fading channels for indoor propagation environments. The derived indoor reference channel model is based on a geometrical scattering model, which consists of an infinite number of scatterers uniformly distributed over the two-dimensional (2D) horizontal plane of a rectangular room. We derive analytical expressions for the probability density function (PDF) of the angle of arrival (AOA), the power delay profile (PDP), and the frequency correlation function (FCF). An efficient sum-of-cisoids (SOC) channel simulator will be derived from the proposed non-realizable reference model. It is shown that the …
Numerical Simulation of Thermal Effects in Coupled Optoelectronic Device-circuit Systems
2008
The control of thermal effects becomes more and more important in modern semiconductor circuits like in the simplified CMOS transceiver representation described by U. Feldmann in the above article Numerical simulation of multiscale models for radio frequency circuits in the time domain. The standard approach for modeling integrated circuits is to replace the semiconductor devices by equivalent circuits consisting of basic elements and resulting in so-called compact models. Parasitic thermal effects, however, require a very large number of basic elements and a careful adjustment of the resulting large number of parameters in order to achieve the needed accuracy.
COMPLEXITY, NOISE AND QUANTUM INFORMATION ON ATOM CHIPS
2008
The realization of quantum logic gates with neutral atoms on atom chips is investigated, including realistic features, such as noise and actual experimental setups.
A General Investigation on the Differential Leakage Factor for Symmetrical and Asymmetrical Multiphase Winding Design
2020
This work provides an investigation based on a fast estimation of the degree of unbalance (D.U.%) and the differential leakage factor (&sigma
Lambda+, the renewal of the Lambda Architecture: Category Theory to the rescue
2021
Designing software architectures for Big Data is a complex task that has to take into consideration multiple parameters, such as the expected functionalities, the properties that are untradeable, or the suitable technologies. Patterns are abstractions that guide the design of architectures to reach the requirements. One of the famous patterns is the Lambda Architecture, which proposes real-time computations with correctness and fault-tolerance guarantees. But the Lambda has also been highly criticized, mostly because of its complexity and because the real-time and correctness properties are each effective in a different layer but not in the overall architecture. Furthermore, its use cases a…
Conceptual design of the TRACE detector readout using a compact, dead time-less analog memory ASIC
2015
[EN] The new TRacking Array for light Charged particle Ejectiles (TRACE) detector system requires monitorization and sampling of all pulses in a large number of channels with very strict space and power consumption restrictions for the front-end electronics and cabling. Its readout system is to be based on analog memory ASICs with 64 channels each that sample a View the MathML source window of the waveform of any valid pulses at 200 MHz while discarding any other signals and are read out at 50 MHz with external ADC digitization. For this purpose, a new, compact analog memory architecture is described that allows pulse capture with zero dead time in any channel while vastly reducing the tota…