Search results for "Field-programmable gate array"
showing 10 items of 175 documents
Wireless versus Wired Network-on-Chip to Enable the Multi- Tenant Multi-FPGAs in Cloud
2021
The new era of computing is not CPU-centric but enriched with all the heterogeneous computing resources including the reconfigurable fabric. In multi-FPGA architecture, either deployed within a data center or as a standalone model, inter-FPGA communication is crucial. Network-on-chip exhibits a promising performance for the integration of one FPGA. A sustainable communication architecture requires stable performance as the number of applications or users grows. Wireless network-on-chip has the potential to be that communication architecture, as it boasts the same performance capability as wired solutions in addition to its multicast capacities. We conducted an exploratory study to investiga…
Feasibility of FPGA accelerated IPsec on cloud
2018
Abstract Hardware acceleration for famous VPN solution, IPsec, has been widely researched already. Still it is not fully covered and the increasing latency, throughput, and feature requirements need further evaluation. We propose an IPsec accelerator architecture in an FPGA and explain the details that need to be considered for a production ready design. This research considers the IPsec packet processing without IKE to be offloaded on an FPGA in an SDN network. Related work performance rates in 64 byte packet size for throughput is 1–2 Gbps with 0.2 ms latency in software, and 1–4 Gbps with unknown latencies for hardware solutions. Our proposed architecture is capable to host 1000 concurre…
PNeuro: A scalable energy-efficient programmable hardware accelerator for neural networks
2018
Proceedings of a meeting held 19-23 March 2018, Dresden, Germany; International audience; Artificial intelligence and especially Machine Learning recently gained a lot of interest from the industry. Indeed, new generation of neural networks built with a large number of successive computing layers enables a large amount of new applications and services implemented from smart sensors to data centers. These Deep Neural Networks (DNN) can interpret signals to recognize objects or situations to drive decision processes. However, their integration into embedded systems remains challenging due to their high computing needs. This paper presents PNeuro, a scalable energy-efficient hardware accelerat…
Multiple register synchronization with a high-speed serial link using the Aurora protocol
2013
In this work, the development and characterization of a multiple synchronous registers interface communicating with a high-speed serial link and using the Aurora protocol is presented. A detailed description of the developing process and the characterization methods and hardware test benches are also included. This interface will implement the slow control busses of the digitizer cards for the second generation of electronics for the Advanced GAmma Tracking Array (AGATA).
Optical Link Card Design for the Phase II Upgrade of TileCal Experiment
2011
This paper presents the design of an optical link card developed in the frame of the R&D activities for the phase 2 upgrade of the TileCal experiment. This board, that is part of the evaluation of different technologies for the final choice in the next years, is designed as a mezzanine that can work independently or be plugged in the optical multiplexer board of the TileCal backend electronics. It includes two SNAP 12 optical connectors able to transmit and receive up to 75 Gb/s and one SFP optical connector for lower speeds and compatibility with existing hardware as the read out driver. All processing is done in a Stratix II GX field-programmable gate array (FPGA). Details are given on th…
Time of flight measurements based on FPGA using a breast dedicated PET
2014
In this work the implementation of a Time-to-Digital Converter (TDC) using a Nutt delay line FPGA-based and applied on a Positron Emission Tomography (PET) device is going to be presented in order to check the system’s suitability for Time of Flight (TOF) measurements. In recent years, FPGAs have shown great advantages for precise time measurements in PET. The architecture employed for these measurements is described in detail. The system developed was tested on a dedicated breast PET prototype, composed of LYSO crystals and Positive Sensitive Photomultipliers (PSPMTs). Two distinct experiments were carried out for this purpose. In the first test, system linearity was evaluated in order to …
Performance of the upgraded PreProcessor of the ATLAS Level-1 Calorimeter Trigger
2020
The PreProcessor of the ATLAS Level-1 Calorimeter Trigger prepares the analogue trigger signals sent from the ATLAS calorimeters by digitising, synchronising, and calibrating them to reconstruct transverse energy deposits, which are then used in further processing to identify event features. During the first long shutdown of the LHC from 2013 to 2014, the central components of the PreProcessor, the Multichip Modules, were replaced by upgraded versions that feature modern ADC and FPGA technology to ensure optimal performance in the high pile-up environment of LHC Run 2. This paper describes the features of the newMultichip Modules along with the improvements to the signal processing achieved.
The MuPix Telescope: A Thin, high Rate Tracking Telescope
2016
The MuPix Telescope is a particle tracking telescope, optimized for tracking low momentum particles and high rates. It is based on the novel High-Voltage Monolithic Active Pixel Sensors (HV-MAPS), designed for the Mu3e tracking detector. The telescope represents a first application of the HV-MAPS technology and also serves as test bed of the Mu3e readout chain. The telescope consists of up to eight layers of the newest prototypes, the MuPix7 sensors, which send data self-triggered via fast serial links to FPGAs, where the data is time-ordered and sent to the PC. A particle hit rate of 1 MHz per layer could be processed. Online tracking is performed with a subset of the incoming data. The ge…
Evaluation of a commercial APD array (Avalanche PhotoDiode) for a readout detector in a hadrontherapy beam characterization application
2010
The aim of the present work is the characterization of the S8898–128–02 Avalanche PhotoDiode array (APDs) from Hamamatsu Photonics. This work includes the implementation of a readout system as well as electronic noise estimation in APDs under several conditions varying integration times and clock frequencies.
A 16 channel high resolution (<11 ps RMS) Time-to-Digital Converter in a Field Programmable Gate Array
2012
A 16-channel Time-to-Digital Converter (TDC) was implemented in a general purpose Field-Programmable Gate Array (FPGA). The fine time calculations are achieved by using the dedicated carry-chain lines. The coarse counter defines the coarse time stamp. In order to overcome the negative effects of temperature and power supply dependency bin-by-bin calibration is applied. The time interval measurements are done using 2 channels. The time resolution of channels are calculated for 1 clock cycle and a minimum of 10.3 ps RMS on two channels, yielding 7.3 ps RMS (10.3 ps/√2) on a single channel is achieved.