Search results for "Field-programmable gate array"
showing 10 items of 175 documents
A real-time non-intrusive FPGA-based drowsiness detection system
2011
Automotive has gained several benefits from the Ambient Intelligent researches involving the deployment of sensors and hardware devices into an intelligent environment surrounding people, meeting users’ requirements and anticipating their needs. One of the main topics in automotive is to anticipate driver needs and safety, in terms of preventing critical and dangerous events. Considering the high number of caused accidents, one of the most relevant dangerous events affecting driver and passengers safety is driver’s drowsiness and hypovigilance. This paper presents a low-intrusive, real-time driver’s drowsiness detection system for common vehicles. The proposed system exploits the ‘‘bright p…
A novel methodology for accelerating bitstream relocation in partially reconfigurable systems
2012
International audience; Xilinx Virtex FPGAs offer the possibility of Partial Reconfiguration (PR). Arbitrary tasks can be allocated and de-allocated onto FPGA without system interruption. However, mapping a task to any available PR region requires a unique partial bitstream for each partition, hence reducing memory storage requirements. In recent years, an interest on overcoming this problem has lead to the concept of Partial Bitstream Relocation (PBR). The principle is to perform bitstream modification to map it to different regions. However, PBR consumes scarce resources in hardware implementations, and introduces a prohibitive time overhead when done in software. In order to find the bes…
Accelerating short read mapping on an FPGA (abstract only)
2012
The explosive growth of short read datasets produced by high throughput DNA sequencing technologies poses a challenge to the mapping of short reads to a reference genome in terms of sensitivity and execution speed. Existing methods often use a restrictive error model for computing the alignments to improve speed, whereas more flexible error models are generally too slow for large-scale applications. Although a number of short read mapping software tools have been proposed, designs based on hardware are relatively rare. In this paper, we present a hybrid system for short read mapping utilizing both software and field programmable gate array (FPGA)-based hardware. The compute intensive semi-g…
Experimental Validation of a Novel Method for Harmonic Mitigation for a Three-Phase Five-Level Cascaded H-Bridges Inverter
2019
In modern high-power electrical drives, the efficiency of the system is a crucial constraint. Moreover, the efficiency of power converters plays a fundamental role in modern applications requiring also a limited weight, such as the electric vehicles and novel more electric aircraft. The reduction of losses pushes for systems with a dc bus and a high number of dc/ac converters, widespread in the vehicle, not burdened by a too expensive data processing system. The purpose of this article is to concur to reduce losses by proposing an innovative selective harmonic mitigation method based on the identification of the working areas where the reference harmonics present lower amplitudes. In partic…
Real-Time Localization of Epileptogenic Foci EEG Signals: An FPGA-Based Implementation
2020
The epileptogenic focus is a brain area that may be surgically removed to control of epileptic seizures. Locating it is an essential and crucial step prior to the surgical treatment. However, given the difficulty of determining the localization of this brain region responsible of the initial seizure discharge, many works have proposed machine learning methods for the automatic classification of focal and non-focal electroencephalographic (EEG) signals. These works use automatic classification as an analysis tool for helping neurosurgeons to identify focal areas off-line, out of surgery, during the processing of the huge amount of information collected during several days of patient monitori…
An AER handshake-less modular infrastructure PCB with x8 2.5Gbps LVDS serial links
2014
Nowadays spike-based brain processing emulation is taking off. Several EU and others worldwide projects are demonstrating this, like SpiNNaker, BrainScaleS, FACETS, or NeuroGrid. The larger the brain process emulation on silicon is, the higher the communication performance of the hosting platforms has to be. Many times the bottleneck of these system implementations is not on the performance inside a chip or a board, but in the communication between boards. This paper describes a novel modular Address-Event-Representation (AER) FPGA-based (Spartan6) infrastructure PCB (the AER-Node board) with 2.5Gbps LVDS high speed serial links over SATA cables that offers a peak performance of 32-bit 62.5…
Experimental analysis with FPGA controller-based of MC PWM techniques for three-phase five level cascaded H-bridge for PV applications
2016
The FPGA represents a valid solution for the design of control systems for inverters adopted in the field of PV systems because of their high flexibility of use. This paper presents an experimental analysis of the MC SPWM techniques for a three-phase, five-level, cascaded H-Bridge inverter with FPGA controller-based. Several control algorithms are implemented by means of the VHDL programming language and the output voltage waveforms obtained from the main PWM techniques are compared in terms of THD%. Simulation and experimental results are analysed, compared and discussed.
Development of the control card for the digitizers of the second generation electronics of AGATA
2012
In this work, the features and development process of the novel control card for the digitizers of AGATA are presented. The board is part of the new hardware proposed for the electronic system of the experiment. In particular, the control card provides the sampling clock for the digitizers, contributes to the synchronization of the digital data and performs the slow control of its associated digitizer cards.
Latest Frontier Technology and Design of the ATLAS Calorimeter Trigger Board Dedicated to Jet Identification for the LHC Run 3
2016
To cope with the enhanced luminosity of the beam delivered by the Large Hadron Collider (LHC) in 2020, the “A Toroidal LHC ApparatuS” (ATLAS) experiment has planned a major upgrade. As part of this, the trigger at Level1 based on calorimeter data will be upgraded to exploit fine-granularity readout using a new system of Feature Extractors, which each use different physics objects for the trigger selection. The article focusses on the jet Feature EXtractor (jFEX) prototype, one of the three types of Feature Extractors. Up to 2 TB/s have to be processed to provide jet identification (including large area jets) and measurements of global variables within few hundred nanoseconds latency budget.…
Commissioning Experience with the ATLAS Level-1 Calorimeter Trigger System
2007
The ATLAS Level-1 Calorimeter Trigger is one of the main elements of the first stage of event selection for the ATLAS experiment at the LHC. The input stage consists of a mixed analogue/digital component taking trigger sums from the ATLAS calorimeters. The trigger logic is performed in a digital, pipelined system with several stages of processing, largely based on FPGAs, which perform programmable algorithms in parallel with a fixed latency to process about 300 Gbyte/s of input data. The real-time output consists of counts of different types of physics objects and energy sums. The production of final modules started in 2006, and installation of these modules and the necessary infrastructure…