Search results for "Field-programmable gate array"
showing 10 items of 175 documents
Ultrascale+ for the new ATLAS calorimeter trigger board dedicated to jet identification
2018
To cope with the expected increase in luminosity at the Large Hadron Collider in 2021, the ATLAS collaboration is planning a major detector upgrade to be installed during Long Shutdown 2. As a part of this, the Level 1 trigger, based on calorimeter data, will be upgraded to exploit the fine granularity readout using a new system of Feature EXtractors (FEXs), which each reconstruct different physics objects for the trigger selection. The Jet FEX (jFEX) is one of three FEXs and has been conceived to identify small/large area jets, large area tau leptons, missing transverse energy and the total sum of the transverse energy. The use of the latest generation Xilinx Field Programmable Gate Array …
Maximum Likelihood Estimation and non-linear least squares fitting with Levenberg-Marquardt Algorithm implementation in FPGA devices for high resolut…
2012
This work compares two possible solutions to achieve a higher resolution in a hodoscope based on Plastic Scintillating Fibers (PSF) by obtaining the point of maximum incidence of the radioactive beam. The two fitting algorithms proposed have been tested and implemented in Field Programmable Gate Array (FPGA) devices. On one hand, a probabilistic model based on the Maximum Likelihood Estimation (MLE) and on the other hand, non-linear least-squares fit with the Levenberg-Marquardt Algorithm (LMA).
Performance and Implementation Modeling of Gated Linear Networks on FPGA for Lossless Image Compression
2020
Over recent years, imaging systems have seen explosive increase in resolution. These trends present a challenge for resource-constrained embedded imaging devices. Efficient image compression is essential to reduce bandwidth consumption and to increase the capability of on-board storage. Especially, for imaging systems where information loss is not allowed, for example, in medical, military and remote sensing imaging systems. This paper explores the use of Gated Linear Networks (GLNs) for development of embedded lossless compression systems. GLNs have proved themselves via PAQ archiver series, that have been ranked among the top across several lossless compression benchmarks. We propose an a…
FPGA Implementation Of Diffusive Realization For A Distributed Control Operator
2010
International audience; We focus on the question of real-time computation for optimal distributed filtering or control applicable to MEMS Arrays. We present an algorithm for the realization of a linear operator solution to a functional equation through its application to a Lyapunov operatorial equation associated to the heat equation in one dimension. It is based on the diffusive realization, and turns to be well suited for fined grained parallel computer architecture as Field Programmable Gate Arrays (FPGA). An effective FPGA implementation has been successfully carried out. Here, we report the main implementation steps and the final measured performances.
Advanced time-stamped total data acquisition control front-end for MeV ion beam microscopy and proton beam writing
2013
Many ion-matter interactions exhibit [email protected] time dependences such as, fluorophore emission quenching and ion beam induced charge (IBIC). Conventional event-mode MeV ion microbeam data acquisition systems discard the time information. Here we describe a fast time-stamping data acquisition front-end based on the concurrent processing capabilities of a Field Programmable Gate Array (FPGA). The system is intended for MeV ion microscopy and MeV ion beam lithography. The speed of the system (>240,000 events s^-^1 for four analogue to digital converters (ADC)) is limited by the ADC throughput and data handling speed of the host computer.
A Novel Embedded Fingerprints Authentication System Based on Singularity Points
2008
In this paper a novel embedded fingerprints authentication system based on core and delta singularity points detection is proposed. Typical fingerprint recognition systems use core and delta singularity points for classification tasks. On the other hand, the available optical and photoelectric sensors give high quality fingerprint images with well defined core and delta points, if they are present. In the proposed system, fingerprint matching is based on singularity points position, orientation, and relative distance detection. As result, fingerprint matching involves the comparison between few features leading to a very fast system with recognition rates comparable to the standard minutiae…
Efficient smart-camera accelerator: A configurable motion estimator dedicated to video codec
2013
Smart cameras are used in a large range of applications. Usually the smart cameras transmit the video or/and extracted information from the video scene, frequently on compressed format to fit with the application requirements. An efficient hardware accelerator that can be adapted and provide the required coding performances according to the events detected in the video, the available network bandwidth or user requirements, is therefore a key element for smart camera solutions. We propose in this paper to focus on a key part of the compression system: motion estimation. We have developed a flexible hardware implementation of the motion estimator based on FPGA component, fully compatible with…
Hardware Implementation of a Configurable Motion Estimator for Adjusting the Video Coding Performances
2012
International audience; Despite the diversity of video compression standard, the motion estimation still remains a key process which is used in most of them. Moreover, the required coding performances (bit-rate, PSNR, image spatial resolution, etc.) depend obviously of the application, the environment and the network communication. The motion estimation can therefore be adapted to fit with these performances. Meanwhile, the real time encoding is required in many applications. In order to reach this goal, we propose in this paper a hardware implementation of the motion estimator which enables the integer motion search algorithms to be modified and the fractional search and variable block siz…
Multiple modular very long instruction word processors based on field programmable gate arrays
2007
Modern field programmable gate array (FPGA) chips, with their large memory capacity and reconfigurability potential, are opening new frontiers in rapid prototyping of embedded systems. With the advent of high-density FPGAs, it is now possible to implement a high-performance very long instruction word (VLIW) processor core in an FPGA. This paper describes research results about enabling the DSP TMS320 C6201 model for real-time image processing applications by exploiting FPGA technology. We present a modular DSP C6201 VHDL model with a variable instruction set. We call this new development a minimum mandatory modules (M3) approach. Our goals are to keep the flexibility of DSP in order to shor…
LABCENTER. A remote laboratory system platform
2011
Abstract A web system server especially suited for remote laboratories has been developed. Typical e-learning systems do not offer the possibility to perform a remote laboratory where real experiments can be done online, accessing real hardware located at the University facilities. Allowing students to connect to hardware systems remotely provides them with additional knowledge about real devices; very often, real laboratory devices are time or space restricted. The proposed LABCENTER platform is a general frame designed for remote laboratories connection. The platform is designed to allow an authorized student to connect to hardware systems. As direct hardware systems allow only a single u…