Search results for "Gate array"
showing 10 items of 185 documents
Hardware implementation of a robust adaptive filter: Two approaches based in High-Level Synthesis design tools
2009
Abstract Adaptive filters are used in a wide range of applications. Impulsive noise affects the proper operation of the filter and the adaptation process. This noise is one of the most damaging types of signal distortion, not always considered when implementing algorithms. Field Programmable Gate Array (FPGA) are widely used for applications where timing requirements are strict. Nowadays, two main design processes can be followed, namely, Hardware Description Language (HDL) and a High Level Synthesis (HLS) design tool for embedded system design. This paper describes the FPGA implementation of an adaptive filter robust to impulsive noise using two approaches based in HLS and the implementati…
FPGA implementation of a fuel cell emulator
2010
Fuel cell based systems are usually tested with the aid of high-cost and complex auxiliary devices. A fuel cell emulator is an attractive solution for preliminary downward system test. The emulator replaces the effective power source saving cost, volume and hydrogen reserve still ensuring high-accuracy of test results. The use of a highperformance fuel cell model is essential for a successful conclusion of the overall design process. Although the proposed emulator is suitable for each fuel cell type and power level, a 10W Proton Exchange Membrane Fuel Cell emulator is designed and tested. An FPGA based controller models the fuel cell steady-state and dynamic behaviour, including temperature…
Fully digital FPGA-based Front-End Electronics for the GALILEO array
2014
In this work we present the fully digital Front End Electronics (FEE) read out system developed for the GALILEO array. The system, developed in collaboration with the Advanced Gamma Tracking Array (AGATA) collaboration, is composed of three main blocks: preamplifiers, digitizers and preprocessing electronics. The slow control system contains a custom Linux driver, a dynamic library and a server implementing network services. The digital processing of the data from the GALILEO germanium detectors has demonstrated the capability to achieve an energy resolution of 1.53‰ at an energy of 1.33 MeV.
A capacitor selector tool for on-board PDN designs in multigigabit applications
2011
This paper presents a capacitor selector software tool for a proper on-board Power Distribution Network (PDN) design in those high-speed applications which have strict requirements on voltage noise up to the first hundreds of megahertz. Current commercial tools for PDN design only offer a manual choice of the capacitor value and their number simulating the board impedance profile. This manual resolution becomes very hard when the design has high power consumption and noise requirements are very strict. The aim of this software is to solve a basic on-board PDN design minimizing the number of "change simulate-analyze" iterations that have to be carried out in the manual PDN design. This softw…
Design of a mezzanine card with bandwidth aggregation for HPGe gamma spectroscopy
2016
In experimental nuclear physics, HPGe segmented detectors are used to provide high energy resolution of the gamma rays. Besides, 4pi configuration is common to get a full coverage of the interaction point and detection of all the products of the collisions. In this type of experiments, the number of electronic channels can be high (>100) and also the sampling frequency of the digitizing system (>100 Msps). This results in a high data rate per channel (> 2 Gbps) and thus a high aggregated bandwidth to process. In principle, this problem can be solved using a parallel data acquisition system where the input channels (commonly arriving through optical fibers) are read and processed accordingly…
Exploring FPGA‐Based Lock‐In Techniques for Brain Monitoring Applications
2017
Functional near‐infrared spectroscopy (fNIRS) systems for e‐health applications usually suffer from poor signal detection, mainly due to a low end‐to‐end signal‐to‐noise ratio of the electronics chain. Lock‐in amplifiers (LIA) historically represent a powerful technique helping to improve performance in such circumstances. In this work a digital LIA system, based on a Zynq® field programmable gate array (FPGA) has been designed and implemented, in an attempt to explore if this technique might improve fNIRS system performance. More broadly, FPGA‐based solution flexibility has been investigated, with particular emphasis applied to digital filter parameters, needed in the digital LIA, and its …
A new preprocessing and control board for the phase 2 electronics of AGATA experiment
2016
The electronics of AGATA HPGe segmented gamma ray detector faces a new challenge in the search of a bigger integration and cost reduction for the phase 2 of the experiment going beyond 45 crystals. This opportunity can be used to introduce a new architecture based on commercial standards while keeping backward compatibility with current electronics. In this sense, new FPGA devices and fast Ethernet links can be used to ease the preprocessing and control task and allowing for processor farms to distribute the processing load. At the same time, modularity should be a key feature of the design in the aim to make it upgradable in time and technology. This paper presents the design of a new prep…
Nanoseconds Timing System Based on IEEE 1588 FPGA Implementation
2019
Clock synchronization procedures are mandatory in most physical experiments where event fragments are readout by spatially dislocated sensors and must be glued together to reconstruct key parameters (e.g. energy, interaction vertex etc.) of the process under investigation. These distributed data readout topologies rely on an accurate time information available at the frontend, where raw data are acquired and tagged with a precise timestamp prior to data buffering and central data collecting. This makes the network complexity and latency, between frontend and backend electronics, negligible within upper bounds imposed by the frontend data buffer capability. The proposed research work describ…
Hardware and firmware developments for the upgrade of the ATLAS Level-1 Central Trigger Processor
2014
The Central Trigger Processor (CTP) is the final stage of the ATLAS first level trigger system which reduces the collision rate of 40 MHz to a Level-1 event rate of 100 kHz. An upgrade of the CTP is currently underway to significantly increase the number of trigger inputs and trigger combinations, allowing additional flexibility for the trigger menu. We present the hardware and FPGA firmware of the newly designed core module (CTPCORE+) module of the CTP, as well as results from a system used for early firmware and software prototyping based on commercial FPGA evaluation boards. First test result from the CTPCORE+ module will also be shown.
Implementing a Margolus Neighborhood Cellular Automata on a FPGA
2003
Margolus neighborhood is the easiest form of designing Cellular Automata Rules with features such as invertibility or particle conserving. In this paper we introduce a notation to describe completely a rule based on this neighborhood and implement it in two ways: The first corresponds to a classical RAM-based implementation, while the second, based on concurrent cells, is useful for smaller systems in which time is a critical parameter. This implementation has the feature that the evolution of all the cells in the design is performed in the same clock cycle.