Search results for "Gate array"
showing 10 items of 185 documents
An MDE Approach for Rapid Prototyping and Implementation of Dynamic Reconfigurable Systems
2015
This article presents a co-design methodology based on RecoMARTE, an extension to the well-known UML MARTE profile, which is used for the specification and automatic generation of Dynamic and Partially Reconfigurable Systems-on-Chip (DRSoC). This endeavor is part of a larger framework in which Model-Driven Engineering (MDE) techniques are extensively used for modeling and via model transformations, generating executable models, which are exploited by implementation tools to create reconfigurable systems. More specifically, the methodological aspects presented in this article are concerned with expediting the conception and implementation of the hardware platform and the integration of corre…
<title>Achieving high performances at lower cost for real-time image rotation by using dynamic reconfiguration</title>
2001
FPGA components are widely used today to perform various algorithms (digital filtering) in real time. The emergence of Dynamically Reconfigurable (DR) FPGAs made it possible to reduce the number of necessary resources to carry out an image processing application (tasks chain). We present in this article an image processing application (image rotation) that exploits the FPGA's dynamic reconfiguration feature. A comparison is undertaken between the dynamic and static reconfiguration by using two criteria, cost and performance criteria. For the sake of testing the validity of our approach in terms of Algorithm and Architecture Adequacy , we realized an AT40K40 based board ARDOISE.
Architectural improvements and FPGA implementation of a multimodel neuroprocessor
2003
Since neural networks (NNs) require an enormous amount of learning time, various kinds of dedicated parallel computers have been developed. In the paper a 2-D systolic array (SA) of dedicated processing elements (PEs) also called systolic cells (SCs) is presented as the heart of a multimodel neural-network accelerator. The instruction set of the SA allows the implementation of several neural algorithms, including error back propagation and a self organizing feature map algorithm. Several special architectural facilities are presented in the paper in order to improve the 2-D SA performance. A swapping mechanism of the weight matrix allows the implementation of NNs larger than 2-D SA. A systo…
An FPGA based Topological Processor Prototype for the ATLAS Level-1 Trigger Upgrade
2012
By 2014 the LHC will collide proton bunches at 14TeV with an increased instantaneous luminosity up to 3·10³⁴cm⁻²s⁻¹. The resulting higher event rate will challenge the existing ATLAS trigger system. A reduction on the trigger rate can be achieved by selecting interesting channels based on their expected decay topology and thus reducing background. This will be achieved by introducing of a new FPGA based module in the Level-1 trigger: the Topological Processor L1Topo. With L1Topo it will be possible for the first time to concentrate detailed information from the entire calorimeters and the muon detector into a single module. L1Topo will receive a total aggregate bandwidth of 1Tb/s. The data …
Ultrascale+ for the new ATLAS calorimeter trigger board dedicated to jet identification
2018
To cope with the expected increase in luminosity at the Large Hadron Collider in 2021, the ATLAS collaboration is planning a major detector upgrade to be installed during Long Shutdown 2. As a part of this, the Level 1 trigger, based on calorimeter data, will be upgraded to exploit the fine granularity readout using a new system of Feature EXtractors (FEXs), which each reconstruct different physics objects for the trigger selection. The Jet FEX (jFEX) is one of three FEXs and has been conceived to identify small/large area jets, large area tau leptons, missing transverse energy and the total sum of the transverse energy. The use of the latest generation Xilinx Field Programmable Gate Array …
Maximum Likelihood Estimation and non-linear least squares fitting with Levenberg-Marquardt Algorithm implementation in FPGA devices for high resolut…
2012
This work compares two possible solutions to achieve a higher resolution in a hodoscope based on Plastic Scintillating Fibers (PSF) by obtaining the point of maximum incidence of the radioactive beam. The two fitting algorithms proposed have been tested and implemented in Field Programmable Gate Array (FPGA) devices. On one hand, a probabilistic model based on the Maximum Likelihood Estimation (MLE) and on the other hand, non-linear least-squares fit with the Levenberg-Marquardt Algorithm (LMA).
Performance and Implementation Modeling of Gated Linear Networks on FPGA for Lossless Image Compression
2020
Over recent years, imaging systems have seen explosive increase in resolution. These trends present a challenge for resource-constrained embedded imaging devices. Efficient image compression is essential to reduce bandwidth consumption and to increase the capability of on-board storage. Especially, for imaging systems where information loss is not allowed, for example, in medical, military and remote sensing imaging systems. This paper explores the use of Gated Linear Networks (GLNs) for development of embedded lossless compression systems. GLNs have proved themselves via PAQ archiver series, that have been ranked among the top across several lossless compression benchmarks. We propose an a…
FPGA Implementation Of Diffusive Realization For A Distributed Control Operator
2010
International audience; We focus on the question of real-time computation for optimal distributed filtering or control applicable to MEMS Arrays. We present an algorithm for the realization of a linear operator solution to a functional equation through its application to a Lyapunov operatorial equation associated to the heat equation in one dimension. It is based on the diffusive realization, and turns to be well suited for fined grained parallel computer architecture as Field Programmable Gate Arrays (FPGA). An effective FPGA implementation has been successfully carried out. Here, we report the main implementation steps and the final measured performances.
Advanced time-stamped total data acquisition control front-end for MeV ion beam microscopy and proton beam writing
2013
Many ion-matter interactions exhibit [email protected] time dependences such as, fluorophore emission quenching and ion beam induced charge (IBIC). Conventional event-mode MeV ion microbeam data acquisition systems discard the time information. Here we describe a fast time-stamping data acquisition front-end based on the concurrent processing capabilities of a Field Programmable Gate Array (FPGA). The system is intended for MeV ion microscopy and MeV ion beam lithography. The speed of the system (>240,000 events s^-^1 for four analogue to digital converters (ADC)) is limited by the ADC throughput and data handling speed of the host computer.
A Novel Embedded Fingerprints Authentication System Based on Singularity Points
2008
In this paper a novel embedded fingerprints authentication system based on core and delta singularity points detection is proposed. Typical fingerprint recognition systems use core and delta singularity points for classification tasks. On the other hand, the available optical and photoelectric sensors give high quality fingerprint images with well defined core and delta points, if they are present. In the proposed system, fingerprint matching is based on singularity points position, orientation, and relative distance detection. As result, fingerprint matching involves the comparison between few features leading to a very fast system with recognition rates comparable to the standard minutiae…