Search results for "Gigabit"
showing 10 items of 20 documents
Latest Frontier Technology and Design of the ATLAS Calorimeter Trigger Board Dedicated to Jet Identification for the LHC Run 3
2016
To cope with the enhanced luminosity of the beam delivered by the Large Hadron Collider (LHC) in 2020, the “A Toroidal LHC ApparatuS” (ATLAS) experiment has planned a major upgrade. As part of this, the trigger at Level1 based on calorimeter data will be upgraded to exploit fine-granularity readout using a new system of Feature Extractors, which each use different physics objects for the trigger selection. The article focusses on the jet Feature EXtractor (jFEX) prototype, one of the three types of Feature Extractors. Up to 2 TB/s have to be processed to provide jet identification (including large area jets) and measurements of global variables within few hundred nanoseconds latency budget.…
Heavy ion SEE test of 2 Gbit DDR3 SDRAM
2011
New generation 2 Gbit DDR3 SDRAMs from Micron, Samsung and Nanya have been tested under heavy ions. SEFIs significantly outweigh random SEU errors even at low LET; however, SEFIs can be mitigated by frequent re-initialization.
Design and testing of the high speed signal densely populated ATLAS calorimeter trigger board dedicate to jet identification
2017
Abstract—The ATLAS experiment has planned a major upgrade in view of the enhanced luminosity of the beam delivered by the Large Hadron Collider (LHC) in 2021. As part of this, the trigger at Level-1 based on calorimeter data will be upgraded to exploit fine-granularity readout using a new system of Feature Extractors (three in total), which each uses different physics objects for the trigger selection. The contribution focusses on the jet Feature EXtractor (jFEX) prototype. Up to a data volume of 2 TB/s has to be processed to provide jet identification (including large area jets) and measurements of global variables within few hundred nanoseconds latency budget. Such requirements translate …
Gigabit Ethernet backbones with active loops
2001
The current standard Ethernet switches are based on the Spanning Tree (ST) protocol. Their most important restriction is that they can not work when the topology has active loops. In fact, the ST protocol selects a tree from the real topology by blocking the links that are not involved in the tree. This restriction produces a network traffic unbalancing behavior saturating those link near the root switch while rest of links will be idle or with a very low utilization. This paper proposes a new transparent switch protocol for Gigabit Ethernet backbones that considerably improves the performance of current ones. The proposed protocol is named ALOR for Active Loops and Optimal Routing. ALOR pr…
SmartARP: merging IP and MAC addressing for low-cost gigabit Ethernet networks
1999
Abstract Address Resolution Protocol (ARP) is one of the key TCP/IP stack protocols, used on LANs to map 32 bit IP addresses into 48 bit hardware addresses. Regular ARP uses MAC layer broadcasts to perform the mapping. In this paper a new server-based ARP extension (smartARP) is proposed, which allows the extension of ARP functionality beyond a single MAC layer broadcast domain. Compared to regular IP router, smartARP together with simple broadcast-filtering switches presents a low-cost alternative for forwarding packets between MAC layer broadcast domains. SmartARP is transparent to existing IP hosts, operates independent of LAN speed, and scales for big networks.
Heavy ion SEE studies on 4-Gbit NAND-Flash memories
2007
Heavy ion SEE studies on three 4-Gbit NAND-flash memory types were performed at the RADEF facility at the University of Jyvaskyla, Finland with particular emphasis on SEFI differentiation. An error classification for complex memory devices is introduced, and respective cross sections are reported.
Concept of virtual machine based high resolution display wall
2014
This paper presents the scalability and hardware dependency problems found in existing solutions in the high resolution display wall domain and proposes a new solution. Authors propose hosting the system that provides the visual content for the display wall inside a virtual machine. In such way any needed configuration of displays and resolutions can be applied to the graphics processing unit simulated by the virtualization system. The frame buffer content of the virtual graphics processing unit is then split, encoded with H.264 and sent over gigabit Ethernet as an RTP stream to the display wall. The display wall is driven by Raspberry Pi embedded devices that receive the stream, decode it …
Do Current Domestic Gigabit Wireless Technologies Fulfill User Requirements for Ultra High Definition Videos?
2017
We present the results from a measurement-based performance evaluation of wireless networks based on IEEE 802.11n and IEEE 802.11ac standards in an indoor environment, with the aim to analyze their performance under high definition streaming video applications. We focus our study on analyzing the highest performance of these standards using off-the-shelf equipment, both with synthetic TCP and UDP traffic to measure the saturation throughput as well as high definition video streams. The measurements have been conducted in the student labs of our university and show good performance for streaming purposes in high definition and also ultra-high definition from a subjective video quality point …
TID and SEE Tests of an Advanced 8 Gbit NAND-Flash Memory
2008
We report on the dose and operational mode dependence of error percentage, stand-by current, erase and write time of 8 Gbit / 4 Gbit NAND-flash memories as well as on their static, dynamic and SEFI cross sections.
The Argo YBJ daq system and the GRID based data transfer
2008
The Argo-YBJ experiment has now reached itsfinal design configuration. The detector system consists of a fullcoverage array (about 5800 square meters) of Resistive PlateChambers (RPCs). The throughput depends on the trigger rateand threshold. The DAQ system must be able to sustain a max-imum transfer rate of the order of 15 MB/s and a high peakdata flow. Data are read out using a typical front-end acquisitionchain built around a custom bus. Specialized electronics have beendesigned and dedicated software has been written to perform thistask. Data are sent to the online farm through a switch exploitinga gigabit ethernet protocol. A solution to transfer data from theYBJ laboratory to the labo…