Search results for "Hardware architecture"
showing 10 items of 120 documents
A Chemical Index Inspired by Biological Plastic Evolution: Valence-Isoelectronic Series of Aromatics
2004
Plastic evolution is a new perspective of the evolutionary process conjugating the effect, on one hand, of the acquired characters and, on the other, of the relationships that emerge among the principle of evolutionary indeterminacy, the principle of morphologic determination, and natural selection. Plastic evolution is applied to design the coordination index Ic. Ic is used to characterize the valence-isoelectronic series of cyclopentadiene, benzene, toluene, and styrene and compared to charge indices for dipole moment. The parameters needed to calculate Ic are minus the standard enthalpy of formation T, molecular surface area S, and molecular weight W. With the exception of the O heteromo…
Characteristic time scale of auroral electrojet data
1994
The structure function of the AE time series shows that the AE time series is self-affine such that the scaling exponent changes at the time scale of approximately 113 (±9) minutes. Autocorrelation function is shown to have scaling properties similar to those of the structure function. From this result it can be deduced that the time scale at which the scaling properties of the AE data change should equal the typical autocorrelation time of these data. We find the typical autocorrelation time of the AE data is 118 (±9) minutes. The characteristic time scale of the AE data appears as a spectral break in their power spectrum at a period of about twice the autocorrelation time.
Design of MOS Current Mode Logic Gates – Computing the Limits of Voltage Swing and Bias Current
2005
Minimizing a quality metric for an MCML gate, such as power-delay product or energy-delay product, requires solving a system of nonlinear equations subject to constraints on both bias current and voltage swing. In this paper, we will show that the limits of the swing and the bias current are affected by the constraints on maximum area and maximum delay. Moreover, methods for computing such limits are presented.
Backoff Hardware Architecture for Inter-FPGA Traffic Management
2017
International audience; Multi-FPGA platforms are considered to be the mostappropriate experimental way to emulate a large Multi-ProcessorSystem-on-Chip based on a Network-on-Chip. However, theuse of a Network-on-Chip in several FPGAs requires inter-FPGA communication links to replace intra-FPGA links betweenrouters. As the ratio of the logic capacity to the number of IOsonly increases slowly with each generation of FPGA, IOs inFPGA are becoming a scare resource. And as there are morerouters than IOs, using a Network-on-Chip requires sharinginter-FPGA links between routers, and sharing an external linkcan lead to bottlenecks. Here, we evaluate the inter-FPGA trafficmanagement using a backoff…
Implementation of Universal Digital Architecture using 3D-NoC for Mobile Terminal
2014
International Conference on Control, Decision and Information Technologies (CoDIT), Ecole Natl Ingenieurs Metz, Metz, FRANCE, NOV 03-05, 2014; International audience; The need to integrate multiple wireless communication protocols into a single low-cost flexible hardware platform is prompted by the increasing number of emerging communication protocols and applications in modern embedded systems. So the current challenge is to design of new digital architectures, in addition to its ability to take over of many functions. In this paper we have identified similarities between the despreader units in Rake receiver and the processor element in FFT-SDF (Fast Fourier Transform-Single path Delay Fe…
Rapid prototyping platform for stream-oriented reconfigurable computing applications
2010
In this paper we present a methodology and tool for rapid prototyping of real time image processing applications. We describe our design flow of multiprocessor system on chip (MPSoC) architectures based on hardware/software components. This methodology provides automated methods to specify, generate the hardware, software, and the architectural interfaces between them. Our methodology starts from system level specification of the application with parallel processes described in C-code. The processes communicate through an abstract channel called streams. We describe also the solution that we proposed to synthesize a custom bus architecture for the reconfigurable computing applications, whic…
Quantum mechanical settings inspired by RLC circuits
2018
In some recent papers several authors used electronic circuits to construct loss and gain systems. This is particularly interesting in the context of PT-quantum mechanics, where this kind of effects appears quite naturally. The electronic circuits used so far are simple, but not so much. Surprisingly enough, a rather trivial RLC circuit can be analyzed with the same perspective and it produces a variety of unexpected results, both from a mathematical and on a physical side. In this paper we show that this circuit produces two biorthogonal bases associated to the Liouville matrix $\Lc$ used in the treatment of its dynamics, with a biorthogonality which is linked to the value of the parameter…
A Design Methodology for Low-Power MCML Ring Oscillators
2007
In this paper, a low-power design method for MCML based ring oscillators is presented. The proposed method takes into account the parasitic capacitances of the MOS transistors. To validate it, some ring oscillators with different oscillation frequencies were designed in a 0.18 mum CMOS technology. SPICE simulations demonstrate the effectiveness of the design method.
Modeling Networks of Probabilistic Memristors in SPICE
2021
Efficient simulation of stochastic memristors and their networks requires novel modeling approaches. Utilizing a master equation to find occupation probabilities of network states is a recent major departure from typical memristor modeling [Chaos, solitons fractals 142, 110385 (2021)]. In the present article we show how to implement such master equations in SPICE – a general purpose circuit simulation program. In the case studies we simulate the dynamics of acdriven probabilistic binary and multi-state memristors, and dc-driven networks of probabilistic binary and multi-state memristors. Our SPICE results are in perfect agreement with known analytical solutions. Examples of LTspice code are…
Self-organizing maps: A new digital architecture
1991
An original hardware architecture implementing the self-organizing feature maps, which is one of the most powerful and efficent neural network algorithm, is presented. The architecture, contrary to the most investigated hardware implementations of neural networks, is a full digital one and it may be easily built by using the standard VLSI techniques.