Search results for "Hardware_LOGICDESIGN"
showing 10 items of 50 documents
FPGA implementation of Spiking Neural Networks
2012
Abstract Spiking Neural Networks (SNN) have optimal characteristics for hardware implementation. They can communicate among neurons using spikes, which in terms of logic resources, means a single bit, reducing the logic occupation in a device. Additionally, SNN are similar in performance compared to other neural Artificial Neural Network (ANN) architectures such as Multilayer Perceptron, and others. SNN are very similar to those found in the biological neural system, having weights and delays as adjustable parameters. This work describes the chosen models for the implemented SNN: Spike Response Model (SRM) and temporal coding is used. FPGA implementation using VHDL language is also describe…
Atypical transistor-based chaotic oscillators: Design, realization, and diversity
2017
In this paper, we show that novel autonomous chaotic oscillators based on one or two bipolar junction transistors and a limited number of passive components can be obtained via random search with suitable heuristics. Chaos is a pervasive occurrence in these circuits, particularly after manual adjustment of a variable resistor placed in series with the supply voltage source. Following this approach, 49 unique circuits generating chaotic signals when physically realized were designed, representing the largest collection of circuits of this kind to date. These circuits are atypical as they do not trivially map onto known topologies or variations thereof. They feature diverse spectra and predom…
Layout influence on microwave performance of graphene field effect transistors
2018
The authors report on an in-depth statistical and parametrical investigation on the microwave performance of graphene FETs on sapphire substrate. The devices differ for the gate-drain/source distance and for the gate length, having kept instead the gate width constant. Microwave S -parameters have been measured for the different devices. Their results demonstrate that the cut-off frequency does not monotonically increase with the scaling of the device geometry and that it exists an optimal region in the gate-drain/source and gate-length space which maximises the microwave performance.
A Compact SPICE Model for Organic TFTs and Applications to Logic Circuit Design
2016
This work introduces a compact DC model developed for organic thin film transistors (OTFTs) and its SPICE implementation. The model relies on a modified version of the gradual channel approximation that takes into account the contact effects, occurring at nonohmic metal/organic semiconductor junctions, modeling them as reverse biased Schottky diodes. The model also comprises channel length modulation and scalability of drain current with respect to channel length. To show the suitability of the model, we used it to design an inverter and a ring oscillator circuit. Furthermore, an experimental validation of the OTFTs has been done at the level of the single device as well as with a discrete-…
Practical design rules for single-channel ultra high-speed dense dispersion management telecommunication systems
2009
International audience; In this work, we establish some efficient and practical design rules for the implementation of single-channel ultra-high speed (>160-Gbit/s) telecommunication systems based on dense dispersion management. Moreover, we analyze some of actual implementation issues such as slope compensation scenario, junction losses, polarization mode dispersion and chromatic dispersion fluctuations.
How to Enrich Description Logics with Fuzziness
2017
International audience; The paper describes the relation between fuzzy and non-fuzzy description logics. It gives an overview about current research in these areas and describes the difference between tasks for description logics and fuzzy logics. The paper also deals with the transformation properties of description logics to fuzzy logics and backwards. While the process of transformation from a description logic to a fuzzy logic is a trivial inclusion, the other way of reducing information from fuzzy logic to description logic is a difficult task, that will be topic of future work.
Smart NeuroCam with High Level Configuration Tool
2017
Thème de la conférence : New Circuits and Systems; International audience
Design and simulation of efficient combinational circuits based on a new XOR structure in QCA technology
2021
AbstractQuantum-dot cellular automata (QCA), due to its unique characteristics like low power consumption, nanoscale design, and high computing speed is considered as an emerging technology, and it can be used as an alternative for CMOS technology in circuit design for quantum computers in the near future. XOR gate has many applications in the design of digital circuits in QCA. In this paper, an efficient novel structure of XOR gate is proposed in QCA. Also, a novel 1-bit comparator circuit, 1-bit full adder, binary to gray and gray to binary convertor code based on the proposed XOR is designed and simulated using QCADesigner 2.0.3. The simulation results demonstrated that the proposed stru…
Le cadre de sante entre logiques d'utilité économique et logiques de soins hospitaliers
2010
The public hospital first line manager has to organize the activity of his care unit on the basis of arbitrations between two systems of logic that come more and more frequently in conflict: - The market logic / the public hospital logic - The care process logic / the patient's path logic - The function logic / the professional logic - The managerial logic / the logic "bureaucratic"
Hold-in, Pull-in and Lock-in Ranges for Phase-locked Loop with Tangential Characteristic of the Phase Detector
2019
In the present paper the phase-locked loop (PLL), an electric circuit widely used in telecommunications and computer architectures is considered. A new modification of the PLL with tangential phase detector characteristic and active proportionally-integrating (PI) filter is introduced. Hold-in, pull-in and lock-in ranges for given circuit are studied rigorously. It is shown that lock-in range of the new PLL model is infinite, compared to the finite lock-in range of the classical PLL. peerReviewed