Search results for "Hardware_MEMORYSTRUCTURES"
showing 10 items of 64 documents
The differences between distributed shared memory caching and proxy caching
2000
The authors discuss the similarities in caching between the extensively studied distributed shared memory systems and the emerging proxy systems. They believe that several of the techniques used in distributed shared memory systems can be adapted and applied to proxy systems.
Memory irradiation measurements for the European SMART-1 spacecraft
2005
Three different types of memory circuits, that are intended to be used on board of the European satellite SMART-1, have been radiation hardness tested according to ESA's specification. Since the satellite is equipped with an electric propulsion engine, the spacecraft will be exposed to radiation during a long time when passing the radiation belt of the Earth. A standard DRAM circuit from SAMSUNG will serve as building block of the mass memory of SMART-1, and has been tested for total dose and proton induced single event upset (SEU). The DRAM memory showed surprisingly good resistance against radiation. The proton SEU cross sections for the radiation tolerant SRAM and FIFO circuits have also…
Sparsity-Driven Digital Terrain Model Extraction
2020
We here introduce an automatic Digital Terrain Model (DTM) extraction method. The proposed sparsity-driven DTM extractor (SD-DTM) takes a high-resolution Digital Surface Model (DSM) as an input and constructs a high-resolution DTM using the variational framework. To obtain an accurate DTM, an iterative approach is proposed for the minimization of the target variational cost function. Accuracy of the SD-DTM is shown in a real-world DSM data set. We show the efficiency and effectiveness of the approach both visually and quantitatively via residual plots in illustrative terrain types.
Modeling Networks of Probabilistic Memristors in SPICE
2021
Efficient simulation of stochastic memristors and their networks requires novel modeling approaches. Utilizing a master equation to find occupation probabilities of network states is a recent major departure from typical memristor modeling [Chaos, solitons fractals 142, 110385 (2021)]. In the present article we show how to implement such master equations in SPICE – a general purpose circuit simulation program. In the case studies we simulate the dynamics of acdriven probabilistic binary and multi-state memristors, and dc-driven networks of probabilistic binary and multi-state memristors. Our SPICE results are in perfect agreement with known analytical solutions. Examples of LTspice code are…
Quantum algorithms for formula evaluation
2010
We survey the recent sequence of algorithms for evaluating Boolean formulas consisting of NAND gates.
Routing quantum information in spin chains
2013
Two different models for performing efficiently routing of a quantum state are presented. Both cases involve an XX spin chain working as data bus and additional spins that play the role of sender and receivers, one of which is selected to be the target of the quantum state transmission protocol via a coherent quantum coupling mechanism making use of local/global magnetic fields. Quantum routing is achieved, in the first of the models considered, by weakly coupling the sender and the receiver to the data bus. In the second model, strong magnetic fields acting on additional spins located between the sender/receiver and the data bus allow us to perform high fidelity routing.
ESB: Ext2 Split Block Device
2012
Solid State Disks (SSDs) start to replace rotating media (hard disks, HDD) in many areas, but are still not as cost efficient concerning capacity to completely replace them. One approach to use their superior performance properties is to use them as a cache for magnetic disks to speed up overall storage operations. In this paper, we present and evaluate a file system level optimization based on ext2. We split metadata and data and store the metadata on a SDD while the data remains on a common HDD. We evaluate our system with filebench under a file server, web server, and web proxy scenario and compare the results with flashcache. We find that many of the scenarios do not contain enough meta…
Heavy ion SEE studies on 4-Gbit NAND-Flash memories
2007
Heavy ion SEE studies on three 4-Gbit NAND-flash memory types were performed at the RADEF facility at the University of Jyvaskyla, Finland with particular emphasis on SEFI differentiation. An error classification for complex memory devices is introduced, and respective cross sections are reported.
European Banking Union and bank risk disclosure: the effects of the Single Supervisory Mechanism
2022
AbstractThis paper provides evidence on the impact of European Banking Union (BU) and the associated Single Supervisory Mechanism (SSM) on the risk disclosure practices of European banks. The onset of BU and the associated rules are considered as an exogenous shock that provides the setting for a natural experiment to analyze the effects of the new supervisory arrangements on bank risk disclosure practices. A Difference-in-Differences approach is adopted, building evidence from the disclosure practices of systemically important banks supervised by the European Central Bank (ECB) and other banks supervised by national regulators over the period 2012–2017. The main findings are that bank risk…
FADaC
2019
Solid state drives (SSDs) implement a log-structured write pattern, where obsolete data remains stored on flash pages until the flash translation layer (FTL) erases them. erase() operations, however, cannot erase a single page, but target entire flash blocks. Since these victim blocks typically store a mix of valid and obsolete pages, FTLs have to copy the valid data to a new block before issuing an erase() operation. This process therefore increases the latencies of concurrent I/Os and reduces the lifetime of flash memory. Data classification schemes identify data pages with similar update frequencies and group them together. FTLs can use this grouping to design garbage collection strategi…