Search results for "Hardware_PERFORMANCEANDRELIABILITY"
showing 10 items of 91 documents
Key Contributions to the Cross Section of NAND Flash Memories Irradiated With Heavy Ions
2008
Heavy-ion irradiation of NAND flash memories under operating conditions leads to errors with complex, data-dependent signatures. We present upsets due to hits in the floating gate array and in the peripheral circuitry, discussing their peculiarities in terms of pattern dependence and annealing. We also illustrate single event functional interruptions, which lead to errors during erase and program operations. To account for all the phenomena we observe during and after irradiation, we propose an ldquoeffective cross section,rdquo which takes into account the array and peripheral circuitry contributions to the SEU sensitivity, as well as the operating conditions.
Fast SWAP gate by adiabatic passage
2005
We present a process for the construction of a SWAP gate which does not require a composition of elementary gates from a universal set. We propose to employ direct techniques adapted to the preparation of this specific gate. The mechanism, based on adiabatic passage, constitutes a decoherence-free method in the sense that spontaneous emission and cavity damping are avoided.
Minimum power-delay product design of MCML gates
2008
This paper describes a methodology for the minimization of the power-delay product of MCML gates. The method is based on the novel concept of crossing point capacitance. The methodology was been validated by designing several gates using in an IBM 130 nm CMOS process.
Quantum mechanical settings inspired by RLC circuits
2018
In some recent papers several authors used electronic circuits to construct loss and gain systems. This is particularly interesting in the context of PT-quantum mechanics, where this kind of effects appears quite naturally. The electronic circuits used so far are simple, but not so much. Surprisingly enough, a rather trivial RLC circuit can be analyzed with the same perspective and it produces a variety of unexpected results, both from a mathematical and on a physical side. In this paper we show that this circuit produces two biorthogonal bases associated to the Liouville matrix $\Lc$ used in the treatment of its dynamics, with a biorthogonality which is linked to the value of the parameter…
A Design Methodology for Low-Power MCML Ring Oscillators
2007
In this paper, a low-power design method for MCML based ring oscillators is presented. The proposed method takes into account the parasitic capacitances of the MOS transistors. To validate it, some ring oscillators with different oscillation frequencies were designed in a 0.18 mum CMOS technology. SPICE simulations demonstrate the effectiveness of the design method.
A Novel Fault-Tolerant Routing Technique for Mesh-of-Tree based Network-on-Chip Design
2018
Due to the increase in the number of processing elements in System-on-Chips (SoCs), communication between the cores is becoming complex. A solution to this issue in SoCs gave rise to a new paradigm called Network-on-Chips (NoCs). In NoCs, communication between different cores is achieved using packet based switching techniques. In the deep sub-micron technology, NoCs are more susceptible to different kinds of faults which can be transient, intermittent and permanent. These faults can occur at any component of NoCs. This paper presents a novel Fault-Tolerant Routing (FTR) technique for Mesh-of-Tree (MoT) topology in the presence of router faults. The proposed technique is compared with routi…
Fault Tolerant Routing Methodology for Mesh-of-Tree based Network-on-Chips using Local Reconfiguration
2018
Increase in the processing elements in a System-on- Chip (SoC) has led to an increasing complexity between the cores in the entire network. This communication bottleneck led to rise in the new paradigm called Network-on-Chip (NoC). These NoC are very much susceptible to various types of faults which can be transient, intermittent or permanent. This paper presents a fault-tolerant routing technique which can route the packets from a source to a destination in presence of permanent faults in the leaf routers of Mesh-of-Tree topology where cores are connected. This is achieved by using reconfiguration in the local ports of the leaf routers by inserting multiplexers as a layer between the leaf …
Architectural Implementation of a Reconfigurable NoC Design for Multi-Applications
2021
With the increasing number of applications running on a Network-on-Chip (NoC) based System-on-Chip (SoC), there is a need for designing a reconfigurable NoC platform to achieve acceptable performance for all the applications. This paper proposes a novel architecture for implementing a reconfiguration logic to the NoC platform executing multiple applications. The proposed architecture reconfigures SoC modules to the routers in the NoC with the help of tri-state buffers based on the applications running. The overhead in implementing the reconfiguration circuitry is significantly less, approximately 0.9% of the area and 1% of the total power consumed by the router network. The architectures pr…
A computer controlled patterning system for scanning probe microscopes
1999
Abstract A pattern generator system for lithography based on scanning force microscopes has been developed. Patterns to be miniaturized onto a chip can be scanned or drawn by any common graphical program. The pattern file is used to control a voltage simultaneously with the microscope probe scanning the surface of the substrate. The voltage can be used in numerous different ways to manipulate the substrate, depending on the lithographic method preferred. We have demonstrated the system by adding this voltage to the z -piezo voltage of the scanner, in order to make the probe plow the pattern into a film spinned on the sample. To maintain linearity in zooming in and rotating the scanning dire…
Logic gates scheme based on Coulomb blockade in metallic nanoclusters with organic ligands
2010
We propose a logic gates scheme based on the electron transfer through metallic nanoclusters linked to organic ligands and discuss theoretically the characteristics needed for practical implementation. As a proof-of-the-concept, we demonstrate the OR, AND and NOT gates and study the performance in terms of temperature, applied voltage, and noise.