Search results for "ICD"

showing 10 items of 102 documents

COMPLEXITY, NOISE AND QUANTUM INFORMATION ON ATOM CHIPS

2008

The realization of quantum logic gates with neutral atoms on atom chips is investigated, including realistic features, such as noise and actual experimental setups.

Condensed Matter::Quantum GasesPhysicsQuantum networkPhysics and Astronomy (miscellaneous)Quantum sensorQuantum simulatorGATESQuantum logicComputer Science::Hardware ArchitectureQuantum circuitQuantum gateQuantum error correctionQuantum mechanicsPhysics::Atomic and Molecular ClustersPhysics::Atomic PhysicsQuantum informationHardware_LOGICDESIGNInternational Journal of Quantum Information
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A Methodology for the Design of MOS Current-Mode Logic Circuits

2010

In this paper, a design methodology for the minimization of various performance metrics of MOS Current-Mode Logic (MCML) circuits is described. In particular, it allows to minimize the delay under a given power consumption, the power consumption under a given delay and the power-delay product. Design solutions can be evaluated graphically or by simple and effective automatic procedures implemented within the MATLAB environment. The methodology exploits the novel concepts of crossing-point current and crossing-point capacitance. A useful feature of it is that it provides the designer with useful insights into the dependence of the performance metrics on design variables and fan-out capacitan…

EngineeringPower–delay productbusiness.industryCircuit designFan-outMOS current-mode logic MCML low-power design power-delay productSettore ING-INF/01 - ElettronicaCapacitanceElectronic Optical and Magnetic MaterialsLow-power electronicsElectronic engineeringCurrent-mode logicElectrical and Electronic EngineeringMATLABbusinesscomputerHardware_LOGICDESIGNcomputer.programming_languageElectronic circuitIEICE Transactions on Electronics
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Optimum design of two-level MCML gates

2008

In this paper, we address the problem of the optimum design of two-level MOS Current Mode Logic (MCML) gates. In particular, we describe a design methodology based on the concept of crossing-point current already introduced for the optimum design of single-level MCML gates. This methodology is suited both for automated implementation and graphic estimate of the optimum design. Moreover, it clearly shows how some important design parameters affect the optimum values of delay and power consumption. Several gates were designed in an IBM 130 nm CMOS technology. The results of SPICE simulations, reported here, demonstrate the effectiveness of the proposed design methodology.

Engineeringbusiness.industryNoise (signal processing)SpiceLogic synthesisCMOSComputer engineeringLogic gateElectronic engineeringCurrent-mode logicIBMbusinessDesign methodsHardware_LOGICDESIGN2008 15th IEEE International Conference on Electronics, Circuits and Systems
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Higher PV Module Efficiency by a Novel CBS Bypass

2011

There is an increasing focus on reducing costs and improving efficiency for photovoltaic (PV) cells and modules as well as finding a more efficient approach to the product manufacturing. This letter introduces an innovative solution to bypass shaded PV cells instead of a traditional Schottky diode, in order to avoid overheating of cells in the case of partial shading. The goal is to reduce the power dissipation and improve the general efficiency of a PV generator. A novel device called cool bypass switch is then presented. It is made up of a Power MOS driven by a controller with the task to charge a storage capacitor. Tests and comparisons with standard Schottky diodes are then performed an…

Engineeringbusiness.industryPhotovoltaic systemElectrical engineeringSchottky diodeMaximum power point trackinglaw.inventionCapacitorSolar cell efficiencyOperating temperaturelawHardware_INTEGRATEDCIRCUITSGrid-connected photovoltaic power systemBypass schottky diode efficiency hot-spot photovoltaic (PV)Electrical and Electronic EngineeringbusinessHardware_LOGICDESIGNDiode
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Vēstījuma paņēmieni un tēlu raksturojums F. S. Ficdžeralda romānā „Lielais Getsbijs”

2015

Pētnieciskajā darbā tiek analizēta vēstījuma paņēmieni, kas izmatoti dažādu tēlu raksturojumam F.S. Ficdžeralda romānā ,,Lielais Getsbijs”. Teorētiskajā daļā ir veikts literatūras pārskats par naratoloģiju un tēlu raksturojumu. Praktiskā daļa tiek fokusēta uz F.S. Ficdžeralda romāna ,,Lielais Getsbijs” analīzi, iekļaujot stāstījuma tehniku, kas izmantota tēlu raksturojumam F.S. Ficdžeralda romānā ,,Lielais Getsbijs”. Darbu noslēdz secinājumi, kas ir balstīti uz teorētisko avotu un F.S. Ficdžeralda romāna ,,Lielais Getsbijs” analīzi. Iegūtie dati dod iespēju atklāt nozīmīgus viedokļus par vēstījuma tehniku, kas pielietota tēlu raksturojumam modernajā literatūrā. Pētījuma rezultātus un secinā…

F.S. FicdžeraldsValodniecībavēstījuma tehnika„Lielais Getsbijs"tēlu raksturojuminaratoloģija
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Reordering Method and Hierarchies for Quantum and Classical Ordered Binary Decision Diagrams

2017

We consider Quantum OBDD model. It is restricted version of read-once Quantum Branching Programs, with respect to "width" complexity. It is known that maximal complexity gap between deterministic and quantum model is exponential. But there are few examples of such functions. We present method (called "reordering"), which allows to build Boolean function $g$ from Boolean Function $f$, such that if for $f$ we have gap between quantum and deterministic OBDD complexity for natural order of variables, then we have almost the same gap for function $g$, but for any order. Using it we construct the total function $REQ$ which deterministic OBDD complexity is $2^{\Omega(n/\log n)}$ and present quantu…

FOS: Computer and information sciencesComputer Science - Computational ComplexityQuantum PhysicsTheoryofComputation_COMPUTATIONBYABSTRACTDEVICESComputer Science::Logic in Computer ScienceComputingMethodologies_SYMBOLICANDALGEBRAICMANIPULATIONFOS: Physical sciencesComputational Complexity (cs.CC)Computer Science::Artificial IntelligenceComputer Science::Computational ComplexityQuantum Physics (quant-ph)Hardware_LOGICDESIGN
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Quantum algorithms for formula evaluation

2010

We survey the recent sequence of algorithms for evaluating Boolean formulas consisting of NAND gates.

FOS: Computer and information sciencesQuantum PhysicsHardware_MEMORYSTRUCTURESFOS: Physical sciencesComputational Complexity (cs.CC)Computer Science::PerformanceComputer Science::Hardware ArchitectureComputer Science - Computational ComplexityComputer Science::Emerging TechnologiesComputer Science - Data Structures and AlgorithmsData Structures and Algorithms (cs.DS)Hardware_ARITHMETICANDLOGICSTRUCTURESQuantum Physics (quant-ph)Computer Science::Operating SystemsHardware_LOGICDESIGN
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FPGA-based embedded Logic Controllers

2014

In general case, reconfigurable logic controllers (RLC) are included into reactive digital embedded systems, carrying out control for several processes proceeding concurrently. The paper presents a practical application of a formal, rule-based specification language in Gentzen sequent logic, which is used as an intermediate textual description of a control interpreted Petri net. On the other hand exactly the same description serves also as logic design expressions, related with different versions of functionally equivalent concurrent state machine models, considered on Register Transfer Level. The symbolic rule-based specification of Petri net-based embedded Logic Controllers (LCs) can be s…

Finite-state machineSequential logicTheoretical computer scienceComputer scienceProgramming languageHardware description languageLogic familycomputer.software_genreProgrammable logic deviceLogic synthesiscomputerHardware_LOGICDESIGNRegister-transfer levelcomputer.programming_languageLogic optimization2014 7th International Conference on Human System Interactions (HSI)
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Multiplexing AER asynchronous channels over LVDS links with flow-control and clock-correction for scalable neuromorphic systems

2017

Paper presented at the 2017 IEEE International Symposium on Circuits and Systems (ISCAS), held in Baltimore, MD, USA, on 28-31 May 2017.

Flow control (data)Neuromorphic Systembusiness.industryComputer scienceVirtual Wiring020208 electrical & electronic engineeringScalable Neuromorphic SystemsScalable Neuromoriphic02 engineering and technologyAddress event representation (AER)Multiplexing020202 computer hardware & architectureHandshakingNeuromorphic engineeringTransmission (telecommunications)Asynchronous communicationEmbedded system0202 electrical engineering electronic engineering information engineeringbusinessField-programmable gate arrayAER (Address Event Representation)Computer hardwareNeuromorphic SystemsHardware_LOGICDESIGN
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Frequency response of Measurement Current Transformers

2008

In this paper the frequency response of two CTs is experimentally evaluated in the range of 30-600 Hz. A theoretical analysis of CTs behavior has been developed by means of the equivalent circuit. It was shown, by an experimental test, that, for the frequency range analyzed, the transformer equivalent circuit is a valid tool for the evaluation of CT performances.

Frequency responseTotal harmonic distortionMaterials scienceTransducerlawPower system harmonicsElectronic engineeringEquivalent circuitIec standardsTransformerCurrent transformerHardware_LOGICDESIGNlaw.invention2008 IEEE Instrumentation and Measurement Technology Conference
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