Search results for "fpga"
showing 10 items of 129 documents
A reconfigurable platform for evaluating the performance of QoS networks
2010
Nowadays, high performance System and Local Area Networks (SAN/LAN) have to serve heterogeneous traffic consisting of information flows with different bandwidth and latency requirements. This makes it necessary to provide Quality of Service (QoS) and optimize the design of network components. In this paper we present a hardware tool designed to analyze the performance of QoS networks, under given traffic conditions and server models. In particular, a reprogrammable multimedia traffic Generator/Monitor platform has been built. This permits prototyping the communication system of a high speed LAN/SAN on a single FPGA device. Hence, it can be used at design to produce more efficient devices. T…
An Scalable matrix computing unit architecture for FPGA and SCUMO user design interface
2019
High dimensional matrix algebra is essential in numerous signal processing and machine learning algorithms. This work describes a scalable square matrix-computing unit designed on the basis of circulant matrices. It optimizes data flow for the computation of any sequence of matrix operations removing the need for data movement for intermediate results, together with the individual matrix operations’ performance in direct or transposed form (the transpose matrix operation only requires a data addressing modification). The allowed matrix operations are: matrix-by-matrix addition, subtraction, dot product and multiplication, matrix-by-vector multiplication, and matrix by scalar multiplication.…
Fully pipelined real time hardware solution for High Efficiency Video Coding (HEVC) intra prediction
2016
International audience; A fully pipelined hardware accelerator for the High Efficiency Video Coding (HEVC) intra prediction is presented in this paper in order to reduce the computation complexity coming with this module and to accelerate the concerned calculations. Two reconfigurable structures are developed in this paper, the first one concerns angular modes and is identified as Processing Element for Angular (PEA) modes, the other is made in order to handle with the Planar mode and is identified as Processing Element for the Planar (PEP) mode. Each structure is repeated in five paths, that our architecture composed of, working in parallel way. This architecture supports all intra predict…
Contribuciones al procesado hardware de la señal para detectores de radiación de alta resolución espacial con lectura por matriz de fotodiodos : dise…
2013
Aplicaciones de física médica y nuclear para el diagnóstico por imagen o la radioterapia de alta precisión, así como otras de carácter industrial, tales como la implantación iónica en microelectrónica, requieren de dispositivos capaces de conocer la posición de un haz de partículas con alta resolución. El detector de radiación utilizado para determinar la posición de interacción de una partícula o de un haz, en éstas y otras aplicaciones físicas, se denomina hodoscopio, y su función es proporcionar la característica espacial del haz. La tecnología basada en fibra óptica centelleadora es una solución al problema de posicionamiento de alta precisión que ha ido adquiriendo importancia en los ú…
PNeuro: A scalable energy-efficient programmable hardware accelerator for neural networks
2018
Proceedings of a meeting held 19-23 March 2018, Dresden, Germany; International audience; Artificial intelligence and especially Machine Learning recently gained a lot of interest from the industry. Indeed, new generation of neural networks built with a large number of successive computing layers enables a large amount of new applications and services implemented from smart sensors to data centers. These Deep Neural Networks (DNN) can interpret signals to recognize objects or situations to drive decision processes. However, their integration into embedded systems remains challenging due to their high computing needs. This paper presents PNeuro, a scalable energy-efficient hardware accelerat…
Backoff Hardware Architecture for Inter-FPGA Traffic Management
2017
International audience; Multi-FPGA platforms are considered to be the mostappropriate experimental way to emulate a large Multi-ProcessorSystem-on-Chip based on a Network-on-Chip. However, theuse of a Network-on-Chip in several FPGAs requires inter-FPGA communication links to replace intra-FPGA links betweenrouters. As the ratio of the logic capacity to the number of IOsonly increases slowly with each generation of FPGA, IOs inFPGA are becoming a scare resource. And as there are morerouters than IOs, using a Network-on-Chip requires sharinginter-FPGA links between routers, and sharing an external linkcan lead to bottlenecks. Here, we evaluate the inter-FPGA trafficmanagement using a backoff…
A hardware skin-segmentation IP for vision based smart ADAS through an FPGA prototyping
2017
International audience; In this paper we presents a platform based design approach for fast HW/SW embedded smart Advanced Driver Assistant System (ADAS) design and prototyping. Then, we share our experience in designing and prototyping a HW/SW vision based smart embedded system as an ADAS that helps to increase the safety of car's drivers. We present a physical prototype of the vision ADAS based on a Zynq FPGA. The system detects the fatigue state of the driver by monitoring the eyes closure and generates a real-time alert. A new HW/SW codesign skin segmentation step to locate the eyes/face is proposed. Our presented new approach migrates the skin segmentation step from processing system (S…
FPGA-piirien hyödyntäminen ultranopeassa automatisoidussa kaupankäynnissä
2012
Ultranopeassa automatisoidussa kaupankäynnissä (HFT) aika on rahaa ja jo millisekunnin etu kilpailijoihin nähden voi tuottaa suurenkin voiton. Optimoinnin HFT-järjestelmän joka osissa nopeuttavat järjestelmää. FPGA-piirien käyttö voi nopeuttaa HFT-järjestelmää huomattavasti. Erityisesti FPGA-piiri soveltuu markkinasyötteen käsittelyyn. FPGA-piireillä savutetaan 5-22 kertainen nopeus yleiskäyttöiseen suorittimeen nähden markkinasyötteen käsittelyssä In high-frequency trading (HFT) time is money. Even a one millisecond advance to other traders can bring huge wins to the HFT system. Optimazations in different parts of the HFT system can make system faster. Using FPGAs signifacantly decreases l…
From UML Specification into FPGA Implementation
2014
In the paper a method of using the Unified Modeling Language for specification of digital systems, especially logic controllers, is presented. The proposed method is based mainly on the UML state machine di- agrams and uses Hierarchical Concurrent Finite State Machines (HCFSMs) as a temporary model. The paper shows a way to transform the UML diagrams, expressed in XML language, to the form that is acceptable by reconfigurable FPGAs (Field Programmable Gate Ar- rays). The UML specification is used to generate an eective program in Hardware Description Languages (HDLs), especially Verilog.
Real-time implementation of counting people in a crowd on the embedded reconfigurable architecture on the unmanned aerial vehicle
2020
The crowd counting task is an important research problem. Now more and more people are concerned about safety issues. Considering the scenario of a crowded scene: a population density system analyzes the crowds and triggers a warning to divert the crowds when their population density exceeds a normal range. With such a system, the incident of the Shanghai New Year's stampede will not happen again. The most difficult problem of population counting at present: On the one hand, in the densely populated area, how to make the model distinguish human head features more finely, such as head overlap. The second aspect is to find a small-scale local head feature in an image with a wide range of popu…