Search results for "integrated circuit"
showing 10 items of 130 documents
Improving topological mapping on NoCs
2010
Networks-on-Chip (NoCs) have been proposed as an efficient solution to the complex communications on System-on-chip (SoCs). The design flow of network-on-chip (NoCs) include several key issues, and one of them is the decision of where cores have to be topologically mapped. This thesis proposes a new approach to the topological mapping strategy for NoCs. Concretely, we propose a new topological mapping technique for regular and irregular NoC platforms and its application for optimizing application specific NoC based on distributed and source routing.
The promise of spintronics for unconventional computing
2021
Novel computational paradigms may provide the blueprint to help solving the time and energy limitations that we face with our modern computers, and provide solutions to complex problems more efficiently (with reduced time, power consumption and/or less device footprint) than is currently possible with standard approaches. Spintronics offers a promising basis for the development of efficient devices and unconventional operations for at least three main reasons: (i) the low-power requirements of spin-based devices, i.e., requiring no standby power for operation and the possibility to write information with small dynamic energy dissipation, (ii) the strong nonlinearity, time nonlocality, and/o…
Unsupervised image processing scheme for transistor photon emission analysis in order to identify defect location
2015
International audience; The study of the light emitted by transistors in a highly scaled complementary metal oxide semiconductor (CMOS) integrated circuit (IC) has become a key method with which to analyze faulty devices, track the failure root cause, and have candidate locations for where to start the physical analysis. The localization of defective areas in IC corresponds to a reliability check and gives information to the designer to improve the IC design. The scaling of CMOS leads to an increase in the number of active nodes inside the acquisition area. There are also more differences between the spot’s intensities. In order to improve the identification of all of the photon emission sp…
A random-walk benchmark for single-electron circuits
2021
Mesoscopic integrated circuits aim for precise control over elementary quantum systems. However, as fidelities improve, the increasingly rare errors and component crosstalk pose a challenge for validating error models and quantifying accuracy of circuit performance. Here we propose and implement a circuit-level benchmark that models fidelity as a random walk of an error syndrome, detected by an accumulating probe. Additionally, contributions of correlated noise, induced environmentally or by memory, are revealed as limits of achievable fidelity by statistical consistency analysis of the full distribution of error counts. Applying this methodology to a high-fidelity implementation of on-dema…
Circuit simulators for circuit analysis in graduate engineering courses
2018
Circuit simulators are extensively used as an aid in many courses at the graduate level in many different engineering and applied sciences programs. SPICE (Simulation Program with Integrated Circuits Emphasis) based software programs have been used for long due to their traditional market position. If we focus on circuits analysis and linear systems subjects, the features that are required from a given simulator can be found in student/limited versions of commercial EDA (Electronic Design Automation) suites or in freeware/open source codes. In this contribution, we analyse and compare the most revelant characteristics of a representative set of the software packages that are commonly adopte…
Analysis and Visualization of Product Memory Layout in IP-XACT
2017
Modern ASIC and FPGA based embedded products use model based design, in which both hardware and software are developed in parallel. Previously HW was completed first and the information handed over to SW team, typically in the form of register tables. The information was even manually copied to SW code, making any changes error-prone and laborious. IP-XACT is the most feasible standard to model HW also for the SW needs. The HW design connectivity and overall memory layout may change due to component instantiations, configurations and conditional operation states, which makes it difficult to create register tables even for documentation. Current register design tools fall short in serving th…
Numerical Simulation of Thermal Effects in Coupled Optoelectronic Device-circuit Systems
2008
The control of thermal effects becomes more and more important in modern semiconductor circuits like in the simplified CMOS transceiver representation described by U. Feldmann in the above article Numerical simulation of multiscale models for radio frequency circuits in the time domain. The standard approach for modeling integrated circuits is to replace the semiconductor devices by equivalent circuits consisting of basic elements and resulting in so-called compact models. Parasitic thermal effects, however, require a very large number of basic elements and a careful adjustment of the resulting large number of parameters in order to achieve the needed accuracy.
GLOBAL DELAY TIME FOR GENERAL DISTRIBUTED NETWORKS WITH APPLICATIONS TO TIMING ANALYSIS OF DIGITAL MOS INTEGRATED CIRCUITS
1989
We consider here a general nerwork composed by n‐distributed parameters lines (with telegraph‐equations models) and m‐capacitors, all connected by a resistive multiport. An asymptotic stability property drives us to define and evaluate a global parameter (“λ‐delay time”) which describes the speed of signals propagation through the network. Because of its simplicity of calculation and its tightness, the given upper bound of the λ‐delay time is useful in timing analysis of MOS integrated chips.
Conceptual design of the TRACE detector readout using a compact, dead time-less analog memory ASIC
2015
[EN] The new TRacking Array for light Charged particle Ejectiles (TRACE) detector system requires monitorization and sampling of all pulses in a large number of channels with very strict space and power consumption restrictions for the front-end electronics and cabling. Its readout system is to be based on analog memory ASICs with 64 channels each that sample a View the MathML source window of the waveform of any valid pulses at 200 MHz while discarding any other signals and are read out at 50 MHz with external ADC digitization. For this purpose, a new, compact analog memory architecture is described that allows pulse capture with zero dead time in any channel while vastly reducing the tota…
Mixed-type circuits with distributed and lumped parameters as correct models for integrated structures
1991
The technology of integrated circuits imposes upon their designers the need to deal with structures with distributed parameters. Figure 4.1 shows a schematic diagram of part of a digital integrated chip, consisting of an n MOS transistor with gate (G), drain (D) and source (S) as terminals, and its thin-film connection with the rest of the chip. This on-chip connection can be made by metals (Al, W), polycristaline silicon (polysilicon) or metal suicides (WSi 2 ). Alternative materials to oxide-passivated silicon substrates are saphire and gallium arsenide (Saraswat and Mohammadi [1982], Yuan et al. [1982], Passlack et al. [1990]).