Search results for "Computer Hardware"
showing 10 items of 378 documents
Design and Implementation of a Low-cost Embedded Iris Recognition System on a Dual-core Processor Platform
2012
Abstract Design of a low-cost embedded iris recognition system is described in this paper. Firstly, we develop a simple and effective iris image acquisition unit, which is cheap and easy to use. This is achieved by both of hardware design and image evaluation algorithm development. Secondly, the iris recognition algorithm is introduced, including iris segmentation, image normalization, feature extraction, and code matching. The algorithm implementation architecture is based on an embedded dual-core processor platform, Texas Instruments TMS320DM6446 evaluation module (Davinci), which contains an ARM core and a DSP core in one chip. Thirdly, the evaluation experiments are performed on the est…
Experiences from a wearable-mobile acquisition system for ambulatory assessment of diet and activity
2017
Public health trends are currently monitored and diagnosed based on large studies that often rely on pen-and-paper data methods that tend to require a large collection campaign. With the pervasiveness of smart-phones and -watches throughout the general population, we argue in this paper that such devices and their built-in sensors can be used to capture such data more accurately with less of an effort. We present a system that targets a pan-European and harmonised architecture, using smartphones and wrist-worn activity loggers to enable the collection of data to estimate sedentary behavior and physical activity, plus the consumption of sugar-sweetened beverages. We report on a unified pilot…
Fault-Tolerant Application Mapping on to ZMesh topology based Network-on-Chip Design
2020
This paper proposes Particle Swarm Optimization (PSO) based fault-tolerant application mapping on to ZMesh topology based Network-on-Chip (NoC) design. Permanent faults in application cores has been considered and performed application mapping using PSO. The major contribution of this paper is to find out the best position for the spare core to be placed in the network using PSO. Experimentations have been carried out by scaling the ZMesh network size and percentage of network faults. The results show that the proposed approach leads to minimum overhead in communication cost over fault-free result.
Feasibility of FPGA accelerated IPsec on cloud
2018
Abstract Hardware acceleration for famous VPN solution, IPsec, has been widely researched already. Still it is not fully covered and the increasing latency, throughput, and feature requirements need further evaluation. We propose an IPsec accelerator architecture in an FPGA and explain the details that need to be considered for a production ready design. This research considers the IPsec packet processing without IKE to be offloaded on an FPGA in an SDN network. Related work performance rates in 64 byte packet size for throughput is 1–2 Gbps with 0.2 ms latency in software, and 1–4 Gbps with unknown latencies for hardware solutions. Our proposed architecture is capable to host 1000 concurre…
PNeuro: A scalable energy-efficient programmable hardware accelerator for neural networks
2018
Proceedings of a meeting held 19-23 March 2018, Dresden, Germany; International audience; Artificial intelligence and especially Machine Learning recently gained a lot of interest from the industry. Indeed, new generation of neural networks built with a large number of successive computing layers enables a large amount of new applications and services implemented from smart sensors to data centers. These Deep Neural Networks (DNN) can interpret signals to recognize objects or situations to drive decision processes. However, their integration into embedded systems remains challenging due to their high computing needs. This paper presents PNeuro, a scalable energy-efficient hardware accelerat…
TID and SEE Tests of an Advanced 8 Gbit NAND-Flash Memory
2008
We report on the dose and operational mode dependence of error percentage, stand-by current, erase and write time of 8 Gbit / 4 Gbit NAND-flash memories as well as on their static, dynamic and SEFI cross sections.
The Regression Tsetlin Machine: A Tsetlin Machine for Continuous Output Problems
2019
The recently introduced Tsetlin Machine (TM) has provided competitive pattern classification accuracy in several benchmarks, composing patterns with easy-to-interpret conjunctive clauses in propositional logic. In this paper, we go beyond pattern classification by introducing a new type of TMs, namely, the Regression Tsetlin Machine (RTM). In all brevity, we modify the inner inference mechanism of the TM so that input patterns are transformed into a single continuous output, rather than to distinct categories. We achieve this by: (1) using the conjunctive clauses of the TM to capture arbitrarily complex patterns; (2) mapping these patterns to a continuous output through a novel voting and n…
High-Energy Electron-Induced SEUs and Jovian Environment Impact
2017
We present experimental evidence of electron-induced upsets in a reference European Space Agency (ESA) single event upset (SEU) monitor, induced by a 200-MeV electron beam at the Very energetic Electronic facility for Space Planetary Exploration in harsh Radiation environments facility at CERN. Comparison of experimental cross sections and simulated cross sections is shown and the differences are analyzed. Possible secondary contributions to the upset rate by neutrons, flash effects, and cumulative dose effects are discussed, showing that electronuclear reactions are the expected SEU mechanism. The ESA Jupiter Icy Moons Explorer mission, to be launched in 2022, presents a challenging radiat…
Management and Control of the Read Out Processors (tpps) of the Aleph Time Projection Chamber
1989
The readout of the Aleph time projection chamber (TPC) relies on a set of 72 time projection processors (TPPs), which are based on a Motorola 68020 microprocessor running a real-time operating system. The advanced processing capabilities of the TPPs allow them to perform in parallel a number of tasks, both during and outside of data acquisition, which are outlined. The management and control of such a large number of intelligent devices is presented. The discussion covers the hardware configuration of the TPPs; the software running the TPPs; their management, status, and control; exception handling and message logging; and the TPP monitoring tasks. >
Multiple register synchronization with a high-speed serial link using the Aurora protocol
2013
In this work, the development and characterization of a multiple synchronous registers interface communicating with a high-speed serial link and using the Aurora protocol is presented. A detailed description of the developing process and the characterization methods and hardware test benches are also included. This interface will implement the slow control busses of the digitizer cards for the second generation of electronics for the Advanced GAmma Tracking Array (AGATA).