Search results for "Converter"

Power Maximization of a PV-Wind HRES via DC-link Voltage Boosting

2009

This paper describes a method for the optimization of a Hybrid Renewable Energy System applied to a low power Photovoltaic-Wind plant. This approach exploits the DC link with a voltage higher than the correspondent value of the batteries, thanks to a suitable DC/DC converter. The goodness of the methodology is firstly proved by means of a novel graphical technique and then verified through numerical simulations. The results are discussed and show that, adopting the proposed technique, a significant increase of the generated power and of the annual energy produced can be achieved.

Performance of the upgraded PreProcessor of the ATLAS Level-1 Calorimeter Trigger

2020

The PreProcessor of the ATLAS Level-1 Calorimeter Trigger prepares the analogue trigger signals sent from the ATLAS calorimeters by digitising, synchronising, and calibrating them to reconstruct transverse energy deposits, which are then used in further processing to identify event features. During the first long shutdown of the LHC from 2013 to 2014, the central components of the PreProcessor, the Multichip Modules, were replaced by upgraded versions that feature modern ADC and FPGA technology to ensure optimal performance in the high pile-up environment of LHC Run 2. This paper describes the features of the newMultichip Modules along with the improvements to the signal processing achieved.

Intraluminal Doppler-sonography: a new device for data analysis and its in vitro test

2002

Summary form only given. A special data acquisition unit has been developed which allows to process on-line not only the mean-phasic Doppler shift signal but also to analyze the spectral contents and the received A-mode signal. The probe consists of a 3f-catheter which is activated by a pulsed transmitter-receiver (Millar). The carrier frequency is 20 MHz and the impulse repetition rate is 62.5 kHz. Two modular A/D converters are used. One digitizes directly the Doppler shift frequencies in the range less than 20 kHz (sampling rate 100 kHz, resolution 12 bit); the other digitizes the RF-signal (sampling rate 200 MHz, resolution 8 bit). For further processing, data are transferred via separa…

A 16 channel high resolution (<11 ps RMS) Time-to-Digital Converter in a Field Programmable Gate Array

2012

A 16-channel Time-to-Digital Converter (TDC) was implemented in a general purpose Field-Programmable Gate Array (FPGA). The fine time calculations are achieved by using the dedicated carry-chain lines. The coarse counter defines the coarse time stamp. In order to overcome the negative effects of temperature and power supply dependency bin-by-bin calibration is applied. The time interval measurements are done using 2 channels. The time resolution of channels are calculated for 1 clock cycle and a minimum of 10.3 ps RMS on two channels, yielding 7.3 ps RMS (10.3 ps/√2) on a single channel is achieved.

On the design of a multiple-output DC/DC converter for the PHI experiment on-board of solar orbiter

2013

Power converters for experiments that have to fly on board space missions (satellite, launchers, etc.) have very stringent requirements due to its use in a very harsh environment. The selection of a suitable topology is therefore not only based on standard requirements but additional more strict ones have also to be fulfilled. This work shows the design procedure followed to build the Power Converter Module (PCM) for the Polarimetric and Helioseismic Imager (SO/PHI), experiment on board the Solar Orbiter Satellite. The selected topology has been a Push-Pull, for a power level of approximately 35 W and with seven output voltages. Galvanic isolation is needed from primary to secondary, but no…

High-Resolution and Low Resource Time To Digital Converters for the KM3NeT Neutrino Telescope

2015

Timing results using an FPGA-based TDC with large arrays of 144 SiPMs

2015

Silicon photomultipliers (SiPMs) have become an alternative to traditional tubes due to several features. However, their implementation to form large arrays is still a challenge especially due to their relatively high intrinsic noise, depending on the chosen readout. In this contribution, two modules composed of SiPMs with an area of roughly mm mm are used in coincidence. Coincidence resolving time (CRT) results with a field-programmable gate array, in combination with a time to digital converter, are shown as a function of both the sensor bias voltage and the digitizer threshold. The dependence of the CRT on the sensor matrix temperature, the amount of SiPM active area and the crystal type…

Frontend electronics for high-precision single photo-electron timing using FPGA-TDCs

2014

Abstract The next generation of high-luminosity experiments requires excellent particle identification detectors which calls for Imaging Cherenkov counters with fast electronics to cope with the expected hit rates. A Barrel DIRC will be used in the central region of the Target Spectrometer of the planned PANDA experiment at FAIR. A single photo-electron timing resolution of better than 100 ps is required by the Barrel DIRC to disentangle the complicated patterns created on the image plane. R&D studies have been performed to provide a design based on the TRB3 readout using FPGA-TDCs with a precision better than 20 ps RMS and custom frontend electronics with high-bandwidth pre-amplifiers and …

Time of flight measurements based on FPGA and SiPMs for PET–MR

2014

Coincidence time measurements with SiPMs have shown to be suitable for PET/MR systems. The present study is based on 3 x 3 mm(2) SiPMs, LSO crystals and a conditioning signal electronic circuit. A Constant Fraction Discriminator (CFD) is used to digitalize the signals and a TDC FPGA-implemented is employed for fine time measurements. TDC capability allows processing the arrival of multiple events simultaneously, measuring times under 100 ps. The complete set-up for time measurements results on a resolution of 892 +/- 41 ps for a pair of detectors. The details of such implementation are exposed and the trade-offs of each configuration are discussed. (C) 2013 Elsevier By, All rights reserved,

MuPix10: First Results from the Final Design

2021

Many years of research and development of High Voltage Monolithic Active Pixel Sensors (HVMAPS) have culminated in the final design for the Mu3e pixel sensor. MuPix10 is a fully monolithic sensor with an active pixel matrix size of $20\times20\,\mathrm{mm}^2$ produced in the $180\,\mathrm{nm}$ HV-CMOS process at TSI Semiconductors. The pixel size is $80\times80\,\mathrm{\mu m}^2$. Hits are read out using a column-drain architecture and sent over up to four serial links with up to $1.6\,\left.\mathrm{Gbit}\middle/\mathrm{s}\right.$ each. By means of DC/DC converters and exclusive usage of on-chip biasing, MuPix10 is fully operable with a minimal set of electrical connections. This is an inte…