Search results for "Gate array"
showing 10 items of 185 documents
Traces of errors due to single ion in floating gate memories
2008
Single, high energy, high LET, ions impacting on a Floating gate array at grazing or near-grazing angles lead to the creation of long traces of FGs with corrupted information. Every time a FG is crossed by a single ion, it experiences a charge loss which permanently degrades the stored information. If the ion crosses more than one FG, the threshold voltage of all those FGs interested by its track will be degraded.
Timing in a FLASH
2017
Abstract A prototype detector, called FLASH (Fast Light Acquiring Start Hodoscope), was built to provide precise Time-of-Flight (TOF) measurements and reference timestamps for detector setups at external beam lines. Radiator bars, made of synthetic fused silica, were coupled to a fast MCP-PMT with 64 channels and read out with custom electronics using Time-over-Threshold (TOT) for signal characterization. The TRB3 system, a high-precision TDC implemented in an FPGA, was used as data acquisition system. The performance of a system consisting of two FLASH units was investigated at a dedicated test experiment at the Mainz Microtron (MAMI) accelerator using its 855 MeV electron beam. The TOT me…
Key Contributions to the Cross Section of NAND Flash Memories Irradiated With Heavy Ions
2008
Heavy-ion irradiation of NAND flash memories under operating conditions leads to errors with complex, data-dependent signatures. We present upsets due to hits in the floating gate array and in the peripheral circuitry, discussing their peculiarities in terms of pattern dependence and annealing. We also illustrate single event functional interruptions, which lead to errors during erase and program operations. To account for all the phenomena we observe during and after irradiation, we propose an ldquoeffective cross section,rdquo which takes into account the array and peripheral circuitry contributions to the SEU sensitivity, as well as the operating conditions.
Pre-production validation of the ATLAS level-1 calorimeter trigger system
2006
The Level-1 Calorimeter Trigger is a major part of the first stage of event selection for the ATLAS experiment at the LHC. It is a digital, pipelined system with several stages of processing, largely based on FPGAs, which perform programmable algorithms in parallel with a fixed latency to process about 300 Gbyte/s of input data. The real-time output consists of counts of different types of trigger objects and energy sums. Prototypes of all module types have been undergoing intensive testing before final production during 2005. Verification of their correct operation has been performed stand-alone and in the ATLAS test-beam at CERN. Results from these investigations will be presented, along …
Upgrade Analog Readout and Digitizing System for ATLAS TileCal Demonstrator
2013
A potential upgrade for the front-end electronics and signal digitization and data acquisition system of the ATLAS hadron calorimeter for the high luminosity Large Hadron Collider (HL-LHC) is described. A Demonstrator is being built to readout a slice of the TileCal detector. The on-detector electronics includes up to 48 Analog Front-end Boards for PMT analog signal processing, 4 Main Boards for data digitization and slow controls, 4 Daughter Boards with high speed optical links to interface the on-detector and off-detector electronics. Two super readout driver boards are used for off-detector data acquisition and fulfilling digital trigger.\n The ATLAS Tile Calorimeter on-detector electron…
A portable readout system for silicon microstrip sensors
2010
Abstract This system can measure the collected charge in one or two microstrip silicon sensors by reading out all the channels of the sensor(s), up to 256. The system is able to operate with different types (p- and n-type) and different sizes (up to 3 cm 2 ) of microstrip silicon sensors, both irradiated and non-irradiated. Heavily irradiated sensors will be used at the Super Large Hadron Collider, so this system can be used to research the performance of microstrip silicon sensors in conditions as similar as possible to the Super Large Hadron Collider operating conditions. The system has two main parts: a hardware part and a software part. The hardware part acquires the sensor signals eith…
Timing results using an FPGA-based TDC with large arrays of 144 SiPMs
2015
Silicon photomultipliers (SiPMs) have become an alternative to traditional tubes due to several features. However, their implementation to form large arrays is still a challenge especially due to their relatively high intrinsic noise, depending on the chosen readout. In this contribution, two modules composed of SiPMs with an area of roughly mm mm are used in coincidence. Coincidence resolving time (CRT) results with a field-programmable gate array, in combination with a time to digital converter, are shown as a function of both the sensor bias voltage and the digitizer threshold. The dependence of the CRT on the sensor matrix temperature, the amount of SiPM active area and the crystal type…
Frontend electronics for high-precision single photo-electron timing using FPGA-TDCs
2014
Abstract The next generation of high-luminosity experiments requires excellent particle identification detectors which calls for Imaging Cherenkov counters with fast electronics to cope with the expected hit rates. A Barrel DIRC will be used in the central region of the Target Spectrometer of the planned PANDA experiment at FAIR. A single photo-electron timing resolution of better than 100 ps is required by the Barrel DIRC to disentangle the complicated patterns created on the image plane. R&D studies have been performed to provide a design based on the TRB3 readout using FPGA-TDCs with a precision better than 20 ps RMS and custom frontend electronics with high-bandwidth pre-amplifiers and …
High resolution Time of Flight determination based on reconfigurable logic devices for future PET/MR systems
2013
Abstract This contribution shows how to perform Time of Flight (TOF) measurements in PET systems using low-cost Field Programmable Gate Array (FPGA) devices with a resolution better of 100 ps. This is achieved with a proper management of the FPGA internal resources and with an extremely careful device calibration process including both temperature and voltage compensation. Preliminary results are reported.
Time of flight measurements based on FPGA and SiPMs for PET–MR
2014
Coincidence time measurements with SiPMs have shown to be suitable for PET/MR systems. The present study is based on 3 x 3 mm(2) SiPMs, LSO crystals and a conditioning signal electronic circuit. A Constant Fraction Discriminator (CFD) is used to digitalize the signals and a TDC FPGA-implemented is employed for fine time measurements. TDC capability allows processing the arrival of multiple events simultaneously, measuring times under 100 ps. The complete set-up for time measurements results on a resolution of 892 +/- 41 ps for a pair of detectors. The details of such implementation are exposed and the trade-offs of each configuration are discussed. (C) 2013 Elsevier By, All rights reserved,