Search results for "Hard"
showing 10 items of 2294 documents
Raman Monitoring of Strain Induced Effects in Mechanically Deposited Single Layer Graphene
2012
Graphene is a two dimensional building block for carbon allotropes of many other dimensionality and shows remarkable electronic and optical properties that attract enormous interest. In order to make graphene useful for real technology, a control of its electronic and mechanical properties is a must. In this respect, a crucial step for the use of graphene layers in device fabrication is the deposition onto suitable substrates, understanding the interaction with them. Micromechanical cleavage of graphite has been used to produce high-quality graphene sheets. The aim of this work is to study the strain effects induced in graphene by the deposition process using Raman spectroscopy and scanning…
Imaginary time propagation code for large-scale two-dimensional eigenvalue problems in magnetic fields
2013
We present a code for solving the single-particle, time-independent Schr\"odinger equation in two dimensions. Our program utilizes the imaginary time propagation (ITP) algorithm, and it includes the most recent developments in the ITP method: the arbitrary order operator factorization and the exact inclusion of a (possibly very strong) magnetic field. Our program is able to solve thousands of eigenstates of a two-dimensional quantum system in reasonable time with commonly available hardware. The main motivation behind our work is to allow the study of highly excited states and energy spectra of two-dimensional quantum dots and billiard systems with a single versatile code, e.g., in quantum …
LaCoDa: Layered connected topology for massive data centers
2017
One of the fundamental challenges of existing data centers is to design a network that interconnects massive number of servers, and therefore providing an efficient and fault-tolerant routing service to upper-layer applications. Several solutions have been proposed (e.g. FatTree, DCell and BCube), however they either scale too fast (i.e., double exponentially) or too slow. This paper proposes a new data center topology, called LaCoDa, that combines the advantages of previous topologies while avoiding their limitations. LaCoDa uses a small node degree that matches physical restriction for servers, and it also interconnects a large number of servers while reducing the wiring complexity and wi…
Exploiting Deductive Processes for Automated Network Management
2005
This paper focuses on improving network management by the adoption of artificial intelligence techniques. We propose a distributed multiagent architecture for network management, which exploits the dynamic reasoning capabilities of the situation calculus in order to emulate the reactive behavior of a human expert to fault situations. The information related to network events is generated by programmable sensors deployed on the network devices and is collected by a logical entity for network managing where it is merged with general domain knowledge, with a view to identifying the root causes of faults and to decide on reparative actions. The logical inference system has been devised to carry…
Fault-Tolerant Application Mapping on to ZMesh topology based Network-on-Chip Design
2020
This paper proposes Particle Swarm Optimization (PSO) based fault-tolerant application mapping on to ZMesh topology based Network-on-Chip (NoC) design. Permanent faults in application cores has been considered and performed application mapping using PSO. The major contribution of this paper is to find out the best position for the spare core to be placed in the network using PSO. Experimentations have been carried out by scaling the ZMesh network size and percentage of network faults. The results show that the proposed approach leads to minimum overhead in communication cost over fault-free result.
Feasibility of FPGA accelerated IPsec on cloud
2018
Abstract Hardware acceleration for famous VPN solution, IPsec, has been widely researched already. Still it is not fully covered and the increasing latency, throughput, and feature requirements need further evaluation. We propose an IPsec accelerator architecture in an FPGA and explain the details that need to be considered for a production ready design. This research considers the IPsec packet processing without IKE to be offloaded on an FPGA in an SDN network. Related work performance rates in 64 byte packet size for throughput is 1–2 Gbps with 0.2 ms latency in software, and 1–4 Gbps with unknown latencies for hardware solutions. Our proposed architecture is capable to host 1000 concurre…
PNeuro: A scalable energy-efficient programmable hardware accelerator for neural networks
2018
Proceedings of a meeting held 19-23 March 2018, Dresden, Germany; International audience; Artificial intelligence and especially Machine Learning recently gained a lot of interest from the industry. Indeed, new generation of neural networks built with a large number of successive computing layers enables a large amount of new applications and services implemented from smart sensors to data centers. These Deep Neural Networks (DNN) can interpret signals to recognize objects or situations to drive decision processes. However, their integration into embedded systems remains challenging due to their high computing needs. This paper presents PNeuro, a scalable energy-efficient hardware accelerat…
On the cellular mechanisms underlying working memory capacity in humans
2016
The cellular processes underlying individual differences in the Working Memory Capacity (WMC) of humans are essentially unknown. Psychological experiments suggest that subjects with lower working memory capacity (LWMC), with respect to subjects with higher capacity (HWMC), take more time to recall items from a list because they search through a larger set of items and are much more susceptible to interference during retrieval. However, a more precise link between psychological experiments and cellular properties is lacking and very difficult to investigate experimentally. In this paper, we investigate the possible underlying mechanisms at the single neuron level by using a computational mod…
A Method for Accurate Measurements of Optimum Noise Parameters of Microwave Transistors
1985
A method for measuring losses of the tuner network used as noise source admittance transformer in transistor noise parameter test-set is presented. Since the method is based on noise figure measurements, tuner losses can be determined on-line while performing measurements for determining transistor noise parameters. As experimental verifications the optimum noise parameters of a GaAs FET in the 4 - 12 GHz frequency range, measured through a computer-assisted measuring system, are reported.
ACCURATE MEASUREMENTS OF OPTIMUM NOISE PARAMETERS OF MICROWAVE TRANSISTORS
1986
A method for measuring losses of the tuner network used as noise source admittance transformer in transistor noise parameter test-set is presented. Since the method is based on noise figure measurements, tuner losses can be determined on-line while performing measurements for determining transistor noise parameters. As experimental verifications the optimum noise parameters of a GaAs FET in the 4 - 12 GHz frequency range, measured through a computer-assisted measuring system, are reported.