Search results for "Hardware_LOGICDESIGN"
showing 10 items of 50 documents
Measuring charge based quantum bits by a superconducting single-electron transistor
2002
Single-electron transistors have been proposed to be used as a read-out device for Cooper pair charge qubits. Here we show that a coupled superconducting transistor at a threshold voltage is much more effective in measuring the state of a qubit than a normal-metal transistor at the same voltage range. The effect of the superconducting gap is to completely block the current through the transistor when the qubit is in the logical state 1, compared to the mere diminishment of the current in the normal-metal case. The time evolution of the system is solved when the measuring device is driven out of equilibrium and the setting is analysed numerically for parameters accessible by lithographic alu…
Arrays of Josephson junctions in an environment with vanishing impedance
1999
The Hamiltonian operator for an unbiased array of Josephson junctions with gate voltages is constructed when only Cooper pair tunnelling and charging effects are taken into account. The supercurrent through the system and the pumped current induced by changing the gate voltages periodically are discussed with an emphasis on the inaccuracies in the Cooper pair pumping. Renormalisation of the Hamiltonian operator is used in order to reliably parametrise the effects due to inhomogeneity in the array and non-ideal gating sequences. The relatively simple model yields an explicit, testable prediction based on three experimentally motivated and determinable parameters.
Geometric quantum computation with Josephson qubits
2001
The quest for large scale integrability and flexibility has stimulated an increasing interest in designing quantum computing devices. A proposal based on small-capacitance Josephson junctions in the charge regime in which quantum gates are implemented by means of adiabatic geometric phases was discussed. The proposed works, are in the charge regime where the qubit is realized by two nearly degenerate charge states of a single electron box.
Fast SWAP gate by adiabatic passage
2005
We present a process for the construction of a SWAP gate which does not require a composition of elementary gates from a universal set. We propose to employ direct techniques adapted to the preparation of this specific gate. The mechanism, based on adiabatic passage, constitutes a decoherence-free method in the sense that spontaneous emission and cavity damping are avoided.
Design of MOS Current Mode Logic Gates – Computing the Limits of Voltage Swing and Bias Current
2005
Minimizing a quality metric for an MCML gate, such as power-delay product or energy-delay product, requires solving a system of nonlinear equations subject to constraints on both bias current and voltage swing. In this paper, we will show that the limits of the swing and the bias current are affected by the constraints on maximum area and maximum delay. Moreover, methods for computing such limits are presented.
Minimum power-delay product design of MCML gates
2008
This paper describes a methodology for the minimization of the power-delay product of MCML gates. The method is based on the novel concept of crossing point capacitance. The methodology was been validated by designing several gates using in an IBM 130 nm CMOS process.
Quantum mechanical settings inspired by RLC circuits
2018
In some recent papers several authors used electronic circuits to construct loss and gain systems. This is particularly interesting in the context of PT-quantum mechanics, where this kind of effects appears quite naturally. The electronic circuits used so far are simple, but not so much. Surprisingly enough, a rather trivial RLC circuit can be analyzed with the same perspective and it produces a variety of unexpected results, both from a mathematical and on a physical side. In this paper we show that this circuit produces two biorthogonal bases associated to the Liouville matrix $\Lc$ used in the treatment of its dynamics, with a biorthogonality which is linked to the value of the parameter…
A Design Methodology for Low-Power MCML Ring Oscillators
2007
In this paper, a low-power design method for MCML based ring oscillators is presented. The proposed method takes into account the parasitic capacitances of the MOS transistors. To validate it, some ring oscillators with different oscillation frequencies were designed in a 0.18 mum CMOS technology. SPICE simulations demonstrate the effectiveness of the design method.
Logic gates scheme based on Coulomb blockade in metallic nanoclusters with organic ligands
2010
We propose a logic gates scheme based on the electron transfer through metallic nanoclusters linked to organic ligands and discuss theoretically the characteristics needed for practical implementation. As a proof-of-the-concept, we demonstrate the OR, AND and NOT gates and study the performance in terms of temperature, applied voltage, and noise.
Numerical approach for signal delay in general distributed networks
2003
The authors consider a general network with telegraph equations modelling distributed elements and having, additionally, nonlinear capacitors. A global asymptotic exponential stability of the solution is given. A simple computable upper bound of the delay time is given. Numerical examples illustrate the usefulness of the results. >