Search results for "AND gate"
showing 10 items of 29 documents
Improving MLC flash performance and endurance with extended P/E cycles
2015
The traditional usage pattern for NAND flash memory is the program/erase (P/E) cycle: the flash pages that make a flash block are all programmed in order and then the whole flash block needs to be erased before the pages can be programmed again. The erase operations are slow, wear out the medium, and require costly garbage collection procedures. Reducing their number is therefore beneficial both in terms of performance and endurance. The physical structure of flash cells limits the number of opportunities to overcome the 1 to 1 ratio between programming and erasing pages: a bit storing a logical 0 cannot be reprogrammed to a logical 1 before the end of the P/E cycle. This paper presents a t…
Comparison of TID response and SEE characterization of single- and multi-level high density NAND flash memories
2009
Heavy ion single-event measurements and total ionizing dose (TID) response for 8Gb commercial NAND flash memories are reported. Radiation results of multilevel flash technology are compared with results from single-level flash technology. The single-level devices are less sensitive to single event upsets (SEUs) than multi-level devices. In general, these commercial high density memories exhibit less TID degradation compared to older generations of flash memories. The charge pump in this study survived up to 600 krads.
Extending SSD lifetime in database applications with page overwrites
2013
Flash-based Solid State Disks (SSDs) have been a great success story over the last years and are widely used in embedded systems, servers, and laptops.One often overlooked ability of NAND flash is that flash pages can be overwritten in certain circumstances. This can be used to decrease wear out and increase performance.In this paper, we analyze the potential of overwrites for the most used data structure in database applications: the B-Tree. We show that with overwrites it is possible to significantly reduce flash wear out and increase overall performance.
Silicon Single Electron Transistors with Single and Multi Dot Characteristics
2000
AbstractSilicon single electron transistors (SET) with side gate have been fabricated on a heavily doped silicon-on-insulator (SOI) substrate. Samples demonstrate two types of characteristics: some of them demonstrate multiple dot behavior and one demonstrates single dot behavior in a wide temperature range. SETs demonstrate oscillations of drain-source current and changes in the width of the Coulomb blockade region with change of gate voltage at least up to 100 K. At temperature below 20 K long-term oscillations (relaxation) of source-drain current after switching the gate voltage has been observed in both multiple dot and single dot samples. Illumination affects both the characteristics o…
Nanocrystal memories for FLASH device applications
2004
Nanocrystals memory cells, in which the conventional polysilicon floating gate is replaced by an array of silicon nanocrystals, have been fabricated and characterized. Single cells and cell arrays of 1 Mb and 10 k have been realized by using a conventional 0.15 μm FLASH technology. Si nanocrystals are deposited on top of tunnel oxide by chemical vapor deposition. Properties of the memory cell have been investigated both for NAND and NOR applications in terms of program/erase window and programming times. Suitable program/erase threshold voltage window can be achieved with fast voltage pulses by adequate choice of tunnel and control dielectric. The feasibility of dual bit storage is also pro…
How far will Silicon nanocrystals push the scaling limits of NVMs technologies?
2004
For the first time, memory devices with optimized high density (2E12#/cm/sup 2/) LPCVD Si nanocrystals have been reproducibly achieved and studied on an extensive statistical basis (from single cell up to 1 Mb test-array) under different programming conditions. An original experimental and theoretical analysis of the threshold voltage shift distribution shows that Si nanocrystals have serious potential to push the scaling of NOR and NAND flash at least to the 35 nm and 65 nm nodes, respectively.
A Structural Model of the Human α7 Nicotinic Receptor in an Open Conformation
2015
International audience; Nicotinic acetylcholine receptors (nAchRs) are ligand-gated ion channels that regulate chemical transmission at the neuromuscular junction. Structural information is available at low resolution from open and closed forms of an eukaryotic receptor, and at high resolution from other members of the same structural family, two prokaryotic orthologs and an eukary- otic GluCl channel. Structures of human channels however are still lacking. Homology modeling and Molecular Dynamics simulations are valuable tools to predict structures of unknown proteins, however, for the case of human nAchRs, they have been unsuccessful in providing a stable open structure so far. This is du…
Effects of high-energy electrons in advanced NAND flash memories
2016
We study the effects of high-energy electrons on advanced NAND Flash memories with multi-level and single-level cell architecture. We analyze the error rate in floating gate cells as a function of electron energy, evaluate the impact of total ionizing dose, and discuss the physical origin of the observed behavior.
Evaluation of Mechanisms in TID Degradation and SEE Susceptibility of Single- and Multi-Level High Density NAND Flash Memories
2011
Heavy ion single-event measurements and total ionizing dose (TID) response for 8 Gb commercial NAND flash memories are reported. Radiation results of multi-level flash technology are compared with results from single-level flash technology. The single-level devices are less sensitive to single event upsets (SEUs) than multi-level devices. In general, these commercial high density memories exhibit less TID degradation compared to older generations of flash memories.
Current Transport Mechanism for Heavy-Ion Degraded SiC MOSFETs
2019
IEEE Transactions on Nuclear Science, 66 (7)