Search results for "Hardware_PERFORMANCEANDRELIABILITY"
showing 10 items of 91 documents
Fault-Tolerant Application Mapping on to ZMesh topology based Network-on-Chip Design
2020
This paper proposes Particle Swarm Optimization (PSO) based fault-tolerant application mapping on to ZMesh topology based Network-on-Chip (NoC) design. Permanent faults in application cores has been considered and performed application mapping using PSO. The major contribution of this paper is to find out the best position for the spare core to be placed in the network using PSO. Experimentations have been carried out by scaling the ZMesh network size and percentage of network faults. The results show that the proposed approach leads to minimum overhead in communication cost over fault-free result.
Methodologies for the Statistical Analysis of Memory Response to Radiation
2016
International audience; Methodologies are proposed for in-depth statistical analysis of Single Event Upset data. The motivation for using these methodologies is to obtain precise information on the intrinsic defects and weaknesses of the tested devices, and to gain insight on their failure mechanisms, at no additional cost. The case study is a 65 nm SRAM irradiated with neutrons, protons and heavy ions. This publication is an extended version of a previous study.
Statistical Analysis of Heavy-Ion Induced Gate Rupture in Power MOSFETs—Methodology for Radiation Hardness Assurance
2012
A methodology for power MOSFET radiation hardness assurance is proposed. It is based on the statistical analysis of destructive events, such as gate oxide rupture. Examples of failure rate calculations are performed.
Studies for low mass, large area monolithic silicon pixel detector modules using the MALTA CMOS pixel chip
2021
Abstract The MALTA monolithic silicon pixel sensors have been used to study dicing and thinning of monolithic silicon pixel detectors for large area and low mass modules. Dicing as close as possible to the active circuitry will allow to build modules with very narrow inactive regions between the sensors. Inactive edge regions of less than 5 μ m to the electronic circuitry could be achieved for 100 μ m thick sensors. The MALTA chip (Cardella et al., 2019) also offers the possibility to transfer data and power directly from chip to chip. Tests have been carried out connecting two MALTA chips directly using ultrasonic wedge wire bonding. Results from lab tests show that the data accumulated in…
Electron-Induced Upsets and Stuck Bits in SDRAMs in the Jovian Environment
2021
This study investigates the response of synchronous dynamic random access memories to energetic electrons and especially the possibility of electrons to cause stuck bits in these memories. Three different memories with different node sizes (63, 72, and 110 nm) were tested. Electrons with energies between 6 and 200 MeV were used at RADiation Effects Facility (RADEF) in Jyvaskyla, Finland, and at Very energetic Electron facility for Space Planetary Exploration missions in harsh Radiative environments (VESPER) in The European Organization for Nuclear Research (CERN), Switzerland. Photon irradiation was also performed in Jyvaskyla. In these irradiation tests, stuck bits originating from electro…
Neutron-induced soft errors in advanced Flash memories
2008
Atmospheric neutrons are a known source of Soft Errors (SE), in static and dynamic CMOS memories. This paper shows for the first time that atmospheric neutrons are able to induce SE in Flash memories as well. Detailed experimental results provide an explanation linking the Floating Gate (FG) cell SE rate to the physics of the neutron-matter interaction. The neutron sensitivity is expected to increase with the number of bits per cell and the reduction of the feature size, but the SE issue is within the limit of current ECC capabilities and will remain so in the foreseeable future.
Measuring charge based quantum bits by a superconducting single-electron transistor
2002
Single-electron transistors have been proposed to be used as a read-out device for Cooper pair charge qubits. Here we show that a coupled superconducting transistor at a threshold voltage is much more effective in measuring the state of a qubit than a normal-metal transistor at the same voltage range. The effect of the superconducting gap is to completely block the current through the transistor when the qubit is in the logical state 1, compared to the mere diminishment of the current in the normal-metal case. The time evolution of the system is solved when the measuring device is driven out of equilibrium and the setting is analysed numerically for parameters accessible by lithographic alu…
Arrays of Josephson junctions in an environment with vanishing impedance
1999
The Hamiltonian operator for an unbiased array of Josephson junctions with gate voltages is constructed when only Cooper pair tunnelling and charging effects are taken into account. The supercurrent through the system and the pumped current induced by changing the gate voltages periodically are discussed with an emphasis on the inaccuracies in the Cooper pair pumping. Renormalisation of the Hamiltonian operator is used in order to reliably parametrise the effects due to inhomogeneity in the array and non-ideal gating sequences. The relatively simple model yields an explicit, testable prediction based on three experimentally motivated and determinable parameters.
Geometric quantum computation with Josephson qubits
2001
The quest for large scale integrability and flexibility has stimulated an increasing interest in designing quantum computing devices. A proposal based on small-capacitance Josephson junctions in the charge regime in which quantum gates are implemented by means of adiabatic geometric phases was discussed. The proposed works, are in the charge regime where the qubit is realized by two nearly degenerate charge states of a single electron box.
Neutron to mirror-neutron oscillations in the presence of mirror magnetic fields
2009
We performed ultracold neutron (UCN) storage measurements to search for additional losses due to neutron (n) to mirror-neutron (n') oscillations as a function of an applied magnetic field B. In the presence of a mirror magnetic field B', UCN losses would be maximal for B = B'. We did not observe any indication for nn' oscillations and placed a lower limit on the oscillation time of tau_{nn'} > 12.0 s at 95% C.L. for any B' between 0 and 12.5 uT.