Search results for "Logic gate"
showing 10 items of 63 documents
Analysis of compressor architectures in MOS current-mode logic
2010
This paper is concerned with the design and the comparison of different compressor architectures for high performance multipliers in MOS current-mode logic (MCML). More specifically, three architectures have been designed for 3-2, 4-2 and 5-2 compressors and two architectures for 7-2 compressors. The various implementations for each type of compressor have been compared one another. This investigation indicates that the architectures based exclusively on three-level MCML gates are the most suitable for MCML implementation in terms of speed, power consumption and area. Design guidelines are provided to improve compressor performance. All the compressors were designed in a TSMC 180nm CMOS tec…
Can Atmospheric Neutrons Induce Soft Errors in NAND Floating Gate Memories?
2009
Atmospheric neutrons can interact with the matter inside a microelectronic chip and generate ionizing particles, which in turn can change the state of one or more memory bits [soft error (SE)]. In this letter, we show that SEs are possible in Flash memories, although with extremely low probabilities. While this problem will increase for future technologies, we do not expect SEs to be the reliability limiting factor for further floating gate scaling.
Optimum design of two-level MCML gates
2008
In this paper, we address the problem of the optimum design of two-level MOS Current Mode Logic (MCML) gates. In particular, we describe a design methodology based on the concept of crossing-point current already introduced for the optimum design of single-level MCML gates. This methodology is suited both for automated implementation and graphic estimate of the optimum design. Moreover, it clearly shows how some important design parameters affect the optimum values of delay and power consumption. Several gates were designed in an IBM 130 nm CMOS technology. The results of SPICE simulations, reported here, demonstrate the effectiveness of the proposed design methodology.
Interference Cancellation for LoRa Gateways and Impact on Network Capacity
2021
In this paper we propose LoRaSyNc (LoRa receiver with SyNchronization and Cancellation), a second generation LoRa receiver that implements Successive Interference Cancellation (SIC) and time synchronization to improve the performance of LoRa gateways. Indeed, the chirp spread spectrum modulation employed in LoRa experiences very high capture probability, and cancelling the strongest signal in case of collisions can significantly improve the cell capacity. An important feature of LoRaSyNc is the ability to track the frequency and clock drifts between the transmitter and receiver, during the whole demodulation of the interfered frame. Due to the use of low-cost oscillators on end-devices, a s…
Improving MLC flash performance and endurance with extended P/E cycles
2015
The traditional usage pattern for NAND flash memory is the program/erase (P/E) cycle: the flash pages that make a flash block are all programmed in order and then the whole flash block needs to be erased before the pages can be programmed again. The erase operations are slow, wear out the medium, and require costly garbage collection procedures. Reducing their number is therefore beneficial both in terms of performance and endurance. The physical structure of flash cells limits the number of opportunities to overcome the 1 to 1 ratio between programming and erasing pages: a bit storing a logical 0 cannot be reprogrammed to a logical 1 before the end of the P/E cycle. This paper presents a t…
Nanoring as logic gate and memory mass device
2015
We study the application of one nanoring driven by a laser field in different states of polarization in logic circuits. In particular we show that assigning boolean values to different state of the incident laser field and to the emitted signals, we can create logic gates such as OR, XOR and AND. we also show the possibility to make logic circuits such as half-adder and full-adder using one and two nanoring respectively. Using two nanorings we made tho Toffoli gate. Finally we use the final angular momentum acquired by the eelctron to store information and hence show the possibility to use and array of nanorings as a mass device.
Progress towards innovative and energy efficient logic circuits
2020
Abstract The integration of superconductive nanowire logic memories and energy efficient computing Josephson logic is explored. Nanowire memories are based on the integration of switchable superconducting nanowires with a suitable magnetic material. These memories exploit the electro-thermal operation of the nanowires to efficiently store and read a magnetic state. In order to achieve proper memory operation a careful design of the nanowire assembly is necessary, as well as a proper choice of the magnetic material to be employed. At present several new superconducting logic families have been proposed, all tending to minimize the effect of losses in the digital Josephson circuits replacing …
Nanoring as logic gate and memory mass device - Poster
Logic gates using nanofluidic diodes based on conical nanopores functionalized with polyprotic acid chains.
2009
Single-track conical nanopores functionalized with polyprotic acid chains have pH-sensitive fixed charge groups and show three levels of conductance that allow integrating several functions on a single nanofluidic diode. Nanometer-scaled pores have previously been employed in separation and sensing but not in logic devices, despite the fact that biological ion channels with pH-dependent fixed charges are known to be responsible for information processing in biophysical structures. As a preliminary application, we propose a logic gate scheme where binary and multivalued logical functions are implemented.
CMOS-compatible field effect nanoscale gas-sensor: Operation and annealing models
2008
Complete modelling of electrically controlled nanoscale gas sensors with Poisson, Wolkenstein, Fokker-Planck and continuity is presented. Based on a plausible Drift explanation we developed suitable models for sensitivity control and operational modes. An onset for CMOS-complying annealing procedures is given.