Search results for "RDW"
showing 10 items of 1401 documents
Exploiting Deductive Processes for Automated Network Management
2005
This paper focuses on improving network management by the adoption of artificial intelligence techniques. We propose a distributed multiagent architecture for network management, which exploits the dynamic reasoning capabilities of the situation calculus in order to emulate the reactive behavior of a human expert to fault situations. The information related to network events is generated by programmable sensors deployed on the network devices and is collected by a logical entity for network managing where it is merged with general domain knowledge, with a view to identifying the root causes of faults and to decide on reparative actions. The logical inference system has been devised to carry…
Fault-Tolerant Application Mapping on to ZMesh topology based Network-on-Chip Design
2020
This paper proposes Particle Swarm Optimization (PSO) based fault-tolerant application mapping on to ZMesh topology based Network-on-Chip (NoC) design. Permanent faults in application cores has been considered and performed application mapping using PSO. The major contribution of this paper is to find out the best position for the spare core to be placed in the network using PSO. Experimentations have been carried out by scaling the ZMesh network size and percentage of network faults. The results show that the proposed approach leads to minimum overhead in communication cost over fault-free result.
Feasibility of FPGA accelerated IPsec on cloud
2018
Abstract Hardware acceleration for famous VPN solution, IPsec, has been widely researched already. Still it is not fully covered and the increasing latency, throughput, and feature requirements need further evaluation. We propose an IPsec accelerator architecture in an FPGA and explain the details that need to be considered for a production ready design. This research considers the IPsec packet processing without IKE to be offloaded on an FPGA in an SDN network. Related work performance rates in 64 byte packet size for throughput is 1–2 Gbps with 0.2 ms latency in software, and 1–4 Gbps with unknown latencies for hardware solutions. Our proposed architecture is capable to host 1000 concurre…
PNeuro: A scalable energy-efficient programmable hardware accelerator for neural networks
2018
Proceedings of a meeting held 19-23 March 2018, Dresden, Germany; International audience; Artificial intelligence and especially Machine Learning recently gained a lot of interest from the industry. Indeed, new generation of neural networks built with a large number of successive computing layers enables a large amount of new applications and services implemented from smart sensors to data centers. These Deep Neural Networks (DNN) can interpret signals to recognize objects or situations to drive decision processes. However, their integration into embedded systems remains challenging due to their high computing needs. This paper presents PNeuro, a scalable energy-efficient hardware accelerat…
On the cellular mechanisms underlying working memory capacity in humans
2016
The cellular processes underlying individual differences in the Working Memory Capacity (WMC) of humans are essentially unknown. Psychological experiments suggest that subjects with lower working memory capacity (LWMC), with respect to subjects with higher capacity (HWMC), take more time to recall items from a list because they search through a larger set of items and are much more susceptible to interference during retrieval. However, a more precise link between psychological experiments and cellular properties is lacking and very difficult to investigate experimentally. In this paper, we investigate the possible underlying mechanisms at the single neuron level by using a computational mod…
A Method for Accurate Measurements of Optimum Noise Parameters of Microwave Transistors
1985
A method for measuring losses of the tuner network used as noise source admittance transformer in transistor noise parameter test-set is presented. Since the method is based on noise figure measurements, tuner losses can be determined on-line while performing measurements for determining transistor noise parameters. As experimental verifications the optimum noise parameters of a GaAs FET in the 4 - 12 GHz frequency range, measured through a computer-assisted measuring system, are reported.
ACCURATE MEASUREMENTS OF OPTIMUM NOISE PARAMETERS OF MICROWAVE TRANSISTORS
1986
A method for measuring losses of the tuner network used as noise source admittance transformer in transistor noise parameter test-set is presented. Since the method is based on noise figure measurements, tuner losses can be determined on-line while performing measurements for determining transistor noise parameters. As experimental verifications the optimum noise parameters of a GaAs FET in the 4 - 12 GHz frequency range, measured through a computer-assisted measuring system, are reported.
TID and SEE Tests of an Advanced 8 Gbit NAND-Flash Memory
2008
We report on the dose and operational mode dependence of error percentage, stand-by current, erase and write time of 8 Gbit / 4 Gbit NAND-flash memories as well as on their static, dynamic and SEFI cross sections.
A Comparison of Special Bonding Techniques for Transmission and Distribution Cables under Normal and Fault Conditions
2021
In this article, a review of the existing special bonding techniques for medium voltage and high-voltage cables is presented. Special bonding techniques have the purpose of reducing sheath currents, thereby limiting copper losses and the reduction of the ampacity of cables. The literature review shows various bonding techniques and how these have evolved over the years thanks to new technologies. Simulations of each technique are performed in MATLAB/Simulink, to compare their strengths and drawbacks both under normal conditions and in the presence of a single-line-to-ground fault.
The Regression Tsetlin Machine: A Tsetlin Machine for Continuous Output Problems
2019
The recently introduced Tsetlin Machine (TM) has provided competitive pattern classification accuracy in several benchmarks, composing patterns with easy-to-interpret conjunctive clauses in propositional logic. In this paper, we go beyond pattern classification by introducing a new type of TMs, namely, the Regression Tsetlin Machine (RTM). In all brevity, we modify the inner inference mechanism of the TM so that input patterns are transformed into a single continuous output, rather than to distinct categories. We achieve this by: (1) using the conjunctive clauses of the TM to capture arbitrarily complex patterns; (2) mapping these patterns to a continuous output through a novel voting and n…