Search results for "Transistor"
showing 10 items of 234 documents
Current Transport Mechanism for Heavy-Ion Degraded SiC MOSFETs
2019
IEEE Transactions on Nuclear Science, 66 (7)
Impact of Terrestrial Neutrons on the Reliability of SiC VD-MOSFET Technologies
2021
Accelerated terrestrial neutron irradiations were performed on different commercial SiC power MOSFETs with planar, trench and double-trench architectures. The results were used to calculate the failure cross-sections and the failure in time (FIT) rates at sea level. Enhanced gate and drain leakage were observed in some devices which did not exhibit a destructive failure during the exposure. In particular, a different mechanism was observed for planar and trench gate MOSFETs, the first showing a partial gate rupture with a leakage path mostly between drain and gate, similar to what was previously observed with heavy-ions, while the second exhibiting a complete gate rupture. The observed fail…
Single-Event Burnout Mechanisms in SiC Power MOSFETs
2018
Heavy ion-induced single-event burnout (SEB) is investigated in high-voltage silicon carbide power MOSFETs. Experimental data for 1200-V SiC power MOSFETs show a significant decrease in SEB onset voltage for particle linear energy transfers greater than 10 MeV/cm 2 /mg, above which the SEB threshold voltage is nearly constant at half of the rated maximum operating voltage for these devices. TCAD simulations show a parasitic bipolar junction transistor turn-on mechanism, which drives the avalanching of carriers and leads to runaway drain current, resulting in SEB. peerReviewed
Enhanced Charge Collection in SiC Power MOSFETs Demonstrated by Pulse-Laser Two-Photon Absorption SEE Experiments
2019
A two-photon absorption technique is used to understand the mechanisms of single-event effects (SEEs) in silicon carbide power metal–oxide–field-effect transistors (MOSFETs) and power junction barrier Schottky diodes. The MOSFETs and diodes have similar structures enabling the identification of effects associated specifically with the parasitic bipolar structure that is present in the MOSFETs, but not the diodes. The collected charge in the diodes varies only with laser depth, whereas it varies with depth and lateral position in the MOSFETs. Optical simulations demonstrate that the variations in collected charge observed are from the semiconductor device structure and not from metal/passiva…
Effect of 20 MeV Electron Radiation on Long Term Reliability of SiC Power MOSFETs
2023
The effect of 20 MeV electron radiation on the lifetime of the silicon carbide power MOSFETs was investigated. Accelerated constant voltage stress (CVS) was applied on the pristine and irradiated devices and time-to-breakdown ( T BD ) and charge-to-breakdown ( Q BD ) of gate oxide were extracted and compared. The effect of electron radiation on the device lifetime reduction can be observed at lower stress gate-to-source voltage ( V GS ) levels. The models of T BD and Q BD dependence on the initial gate current ( I G0 ) are proposed which can be used to describe the device breakdown behaviour. peerReviewed
Proton irradiation-induced reliability degradation of SiC power MOSFET
2023
The effect of 53 MeV proton irradiation on the reliability of silicon carbide power MOSFETs was investigated. Post-irradiation gate voltage stress was applied and early failures in time-dependent dielectric breakdown (TDDB) test were observed for irradiated devices. The applied drain voltage during irradiation affects the degradation probability observed by TDDB tests. Proton-induced single event burnouts (SEB) were observed for devices which were biased close to their maximum rated voltage. The secondary particle production as a result of primary proton interaction with the device material was simulated with the Geant4-based toolkit. peerReviewed
Concatenated logic functions using nanofluidic diodes with all-electrical inputs and outputs
2018
[EN] Nanopore-based logical schemes in ionic solutions typically involve single gates and chemical inputs. The design of computer-like functions requires the consecutive concatenation of several gates and the use of electrical potentials and currents to facilitate the downstream transfer of electrochemical information. We have demonstrated the robust operation of concatenated logic functions using biomimetic nanofluidic diodes based on single pore membranes. To this end, we have implemented first the logic functions AND and OR with combinations of single nanopores using all-electrical input and output signals. The concatenation of these gates allows the output of the OR gate to act as one o…
Self-Healing of Redundant FLASH ADCs
2022
For the design of high-speed ADCs, the traditional speed-accuracy trade-off can only be solved at the expense of power consumption. Using fast small transistors takes full advantage of technology scaling but induces large amounts of random variability. Redundancy has been proposed as a way to cope with variability in FLASH converter and open the trade-off. The offset of redundant comparators are measured and only the best candidates which have been selected are powered-up. However, the candidate selection is usually carried out in foreground and a lot of silicon area is thus occupied by comparators that will only be used once, during calibration. In this paper we show how such an approach, …
On the optimal design of multi-stage cascaded transistor amplifiers with noise, gain and mismatch constraints
2007
The problem of evaluating the optimal performances of cascaded, unbalanced, multi-stage transistor amplifiers is addressed. In particular, a theoretically rigorous approach is proposed for the determination of a family of Optimal Design Curves (ODC's) which express the best noise-gain tradeoff that can be achieved - at each frequency and device operating condition - when a simultaneous constraint on amplifier input VSWR is accounted for. Such curves can be used as a more meaningful starting point in practical amplifier design in place of the approximate calculations so far employed for target performance or optimization goals determination.
On the Theoretical Limits of Noise-Gain-Mismatch Tradeoff in the Design of Multi-Stage Cascaded Transistor Amplifiers
2007
The problem of evaluating the limit performances of cascaded single-ended multi-stage transistor amplifiers is addressed. In particular, a theoretically rigorous approach is proposed for the determination of a family of optimal design curves (ODC's) which express the best (maximum optimal) noise-gain tradeoff that can be achieved - at each operating frequency - when a simultaneous constraint on amplifier input VSWR is accounted for.