Search results for "Flash memory"
showing 10 items of 15 documents
Impact of the erase algorithms on flash memory lifetime
2017
This paper presents a comparative study on the impact of the erase algorithm on flash memory lifetime, to demonstrate how the reduction of overall stress, suffered by memories, will increase their lifetime, thanks to a smart management of erase operations. To this purpose a fixed erase voltage, equal to the maximum value and the maximum time-window, was taken as the reference test; while an algorithm with adaptive voltage levels and the same overall time-window was designed and implemented in order to compare their experimental results. This study was carried out by using an innovative Automated Test Equipment, named Portable-ATE, tailored for Memory Test Chip and designed for performance e…
Compact instrumentation for radiation tolerance test of flash memories in space environment
2010
Aim of this work is the description of a test equipment, designed to be integrated on board of a microsatellite, able to investigate the radiation tolerance of non-volatile memory arrays in a real flight experiment. An FPGA-based design was adopted to preserve a high flexibility degree. Besides standard Program/Read/Erase functions, additional features such as failure data screening and latch-up protection have been implemented. The instrument development phase generated, as a by-product, a non-rad-hard version of the instrument that allowed performing in-situ experiments using 60Co and 10 MeV Boron irradiation facilities on Ground. Preliminary measurement results are reported to show the i…
Can Atmospheric Neutrons Induce Soft Errors in NAND Floating Gate Memories?
2009
Atmospheric neutrons can interact with the matter inside a microelectronic chip and generate ionizing particles, which in turn can change the state of one or more memory bits [soft error (SE)]. In this letter, we show that SEs are possible in Flash memories, although with extremely low probabilities. While this problem will increase for future technologies, we do not expect SEs to be the reliability limiting factor for further floating gate scaling.
Heavy ion SEE studies on 4-Gbit NAND-Flash memories
2007
Heavy ion SEE studies on three 4-Gbit NAND-flash memory types were performed at the RADEF facility at the University of Jyvaskyla, Finland with particular emphasis on SEFI differentiation. An error classification for complex memory devices is introduced, and respective cross sections are reported.
FADaC
2019
Solid state drives (SSDs) implement a log-structured write pattern, where obsolete data remains stored on flash pages until the flash translation layer (FTL) erases them. erase() operations, however, cannot erase a single page, but target entire flash blocks. Since these victim blocks typically store a mix of valid and obsolete pages, FTLs have to copy the valid data to a new block before issuing an erase() operation. This process therefore increases the latencies of concurrent I/Os and reduces the lifetime of flash memory. Data classification schemes identify data pages with similar update frequencies and group them together. FTLs can use this grouping to design garbage collection strategi…
An Analysis of Flash Page Reuse With WOM Codes
2018
Flash memory is prevalent in modern servers and devices. Coupled with the scaling down of flash technology, the popularity of flash memory motivates the search for methods to increase flash reliability and lifetime. Erasures are the dominant cause of flash cell wear, but reducing them is challenging because flash is a write-once medium— memory cells must be erased prior to writing. An approach that has recently received considerable attention relies on write-once memory (WOM) codes, designed to accommodate additional writes on write-once media. However, the techniques proposed for reusing flash pages with WOM codes are limited in their scope. Many focus on the coding theory alone, whereas o…
Improving MLC flash performance and endurance with extended P/E cycles
2015
The traditional usage pattern for NAND flash memory is the program/erase (P/E) cycle: the flash pages that make a flash block are all programmed in order and then the whole flash block needs to be erased before the pages can be programmed again. The erase operations are slow, wear out the medium, and require costly garbage collection procedures. Reducing their number is therefore beneficial both in terms of performance and endurance. The physical structure of flash cells limits the number of opportunities to overcome the 1 to 1 ratio between programming and erasing pages: a bit storing a logical 0 cannot be reprogrammed to a logical 1 before the end of the P/E cycle. This paper presents a t…
Comparison of TID response and SEE characterization of single- and multi-level high density NAND flash memories
2009
Heavy ion single-event measurements and total ionizing dose (TID) response for 8Gb commercial NAND flash memories are reported. Radiation results of multilevel flash technology are compared with results from single-level flash technology. The single-level devices are less sensitive to single event upsets (SEUs) than multi-level devices. In general, these commercial high density memories exhibit less TID degradation compared to older generations of flash memories. The charge pump in this study survived up to 600 krads.
Nanocrystal memories for FLASH device applications
2004
Nanocrystals memory cells, in which the conventional polysilicon floating gate is replaced by an array of silicon nanocrystals, have been fabricated and characterized. Single cells and cell arrays of 1 Mb and 10 k have been realized by using a conventional 0.15 μm FLASH technology. Si nanocrystals are deposited on top of tunnel oxide by chemical vapor deposition. Properties of the memory cell have been investigated both for NAND and NOR applications in terms of program/erase window and programming times. Suitable program/erase threshold voltage window can be achieved with fast voltage pulses by adequate choice of tunnel and control dielectric. The feasibility of dual bit storage is also pro…
TID and SEE Tests of an Advanced 8 Gbit NAND-Flash Memory
2008
We report on the dose and operational mode dependence of error percentage, stand-by current, erase and write time of 8 Gbit / 4 Gbit NAND-flash memories as well as on their static, dynamic and SEFI cross sections.