Search results for "threshold voltage"
showing 10 items of 24 documents
How far will Silicon nanocrystals push the scaling limits of NVMs technologies?
2004
For the first time, memory devices with optimized high density (2E12#/cm/sup 2/) LPCVD Si nanocrystals have been reproducibly achieved and studied on an extensive statistical basis (from single cell up to 1 Mb test-array) under different programming conditions. An original experimental and theoretical analysis of the threshold voltage shift distribution shows that Si nanocrystals have serious potential to push the scaling of NOR and NAND flash at least to the 35 nm and 65 nm nodes, respectively.
A subthreshold, low-power, RHBD reference circuit, for earth observation and communication satellites
2015
A low-power, wide temperature range, radiation tolerant CMOS voltage reference is presented. The proposed reference circuit exhibits a voltage deviation of 0.8mV for 3-MeV protons total ionization dose of 2Mrad and a voltage deviation of 3.8mV for 10-keV X-rays total ionization dose of 4Mrad while being biased at the nominal supply voltage of 0.75V during X-ray irradiation. In addition, the circuit consumes only 4μW and exhibits a measured Temperature Drift of 15ppm/°C for a temperature range of 190°C (−60°C to 130°C) at the supply voltage of 0.75V. It utilizes only CMOS transistors, operating in the subthreshold regime, and poly-silicon resistors without using any diodes or external compon…
Experimental Analysis of the Multipactor Effect With RF Pulsed Signals
2015
The main goal of this letter is the analysis of the multipactor effect within a coaxial waveguide excited by an RF pulsed signal. The variation of the multipactor RF voltage thresholdwiththe ON interval length of the pulse has been analyzed. To reach this aim, an in-house multipactor simulation code based on the Monte-Carlo algorithm has been implemented. The numerical simulations show that the multipactor RF voltage threshold increases as the ON pulse interval diminishes. In addition, an experiment was carried out to validate the proposed theoretical model, and demonstrating the excellent agreement between the theory and the experimental data. Finally, the results are compared with the 20-…
Memory effects in MOS devices based on Si quantum dots
2003
Silicon quantum dots have been deposited on top of a 3-nm tunnel oxide by Low Pressure Chemical Vapour Deposition (LPCVD) and coated with a 7-nm Chemical Vapour Deposited (CVD) oxide. This stack was then incorporated in Metal-Oxide-Semiconductor structure and used as floating gate of a memory cell. The presence of 3 nm of tunnel oxides allows the injection of the charge by direct tunnel (DT) using low voltages for both program and erase operations. The charge stored in the quantum dots is able to produce a well-detectable flat band shift in the capacitors or, equivalently, a threshold voltage shift in the transistors. Furthermore, due to the presence of SiO 2 between the grains, the lateral…
Impact of contact resistance on the electrical properties of MoS
2016
Molybdenum disulphide (MoS2) is currently regarded as a promising material for the next generation of electronic and optoelectronic devices. However, several issues need to be addressed to fully exploit its potential for field effect transistor (FET) applications. In this context, the contact resistance, R C, associated with the Schottky barrier between source/drain metals and MoS2 currently represents one of the main limiting factors for suitable device performance. Furthermore, to gain a deeper understanding of MoS2 FETs under practical operating conditions, it is necessary to investigate the temperature dependence of the main electrical parameters, such as the field effect mobility (μ) a…
Effects of high-energy electrons in advanced NAND flash memories
2016
We study the effects of high-energy electrons on advanced NAND Flash memories with multi-level and single-level cell architecture. We analyze the error rate in floating gate cells as a function of electron energy, evaluate the impact of total ionizing dose, and discuss the physical origin of the observed behavior.
Single-Event Burnout Mechanisms in SiC Power MOSFETs
2018
Heavy ion-induced single-event burnout (SEB) is investigated in high-voltage silicon carbide power MOSFETs. Experimental data for 1200-V SiC power MOSFETs show a significant decrease in SEB onset voltage for particle linear energy transfers greater than 10 MeV/cm 2 /mg, above which the SEB threshold voltage is nearly constant at half of the rated maximum operating voltage for these devices. TCAD simulations show a parasitic bipolar junction transistor turn-on mechanism, which drives the avalanching of carriers and leads to runaway drain current, resulting in SEB. peerReviewed
Ionizing radiation effects on Non Volatile Read Only Memory cells
2012
Threshold voltage (V-th) and drain-source current (I-DS) behaviour of nitride read only memories (NROM) were studied both in situ during irradiation or after irradiation with photons and ions. V-th loss fluctuations are well explained by the same Weibull statistics regardless of the irradiation species and total dose. Results of drain current measurements in-situ during irradiation with photons and ions reveal a step-like increase of I-DS with the total irradiation dose. A brief physical explanation is also provided.
Measuring charge based quantum bits by a superconducting single-electron transistor
2002
Single-electron transistors have been proposed to be used as a read-out device for Cooper pair charge qubits. Here we show that a coupled superconducting transistor at a threshold voltage is much more effective in measuring the state of a qubit than a normal-metal transistor at the same voltage range. The effect of the superconducting gap is to completely block the current through the transistor when the qubit is in the logical state 1, compared to the mere diminishment of the current in the normal-metal case. The time evolution of the system is solved when the measuring device is driven out of equilibrium and the setting is analysed numerically for parameters accessible by lithographic alu…
Traces of errors due to single ion in floating gate memories
2008
Single, high energy, high LET, ions impacting on a Floating gate array at grazing or near-grazing angles lead to the creation of long traces of FGs with corrupted information. Every time a FG is crossed by a single ion, it experiences a charge loss which permanently degrades the stored information. If the ion crosses more than one FG, the threshold voltage of all those FGs interested by its track will be degraded.