0000000000008983
AUTHOR
D. Corso
showing 16 related works from this author
Effect of high-k materials in the control dielectric stack of nanocrystal memories
2004
In this paper we studied program/erase characteristics by FN tunneling in Si nanocrystal memories. Starting from a very good agreement between experimental data and simulations in the case of a memory cell with a thin tunnel oxide, Silicon dots as medium for charge storage, and a CVD silicon dioxide used as control dielectric, we present estimated values of the charge trapping when a high-k material is present in the control dielectric. We then show preliminary results of nanocrystal memories with control dielectric containing high-k materials. ©2004 IEEE.
Ionizing radiation effects on Non Volatile Read Only Memory cells
2012
Threshold voltage (V-th) and drain-source current (I-DS) behaviour of nitride read only memories (NROM) were studied both in situ during irradiation or after irradiation with photons and ions. V-th loss fluctuations are well explained by the same Weibull statistics regardless of the irradiation species and total dose. Results of drain current measurements in-situ during irradiation with photons and ions reveal a step-like increase of I-DS with the total irradiation dose. A brief physical explanation is also provided.
La legge di Okun e le trasformazioni del Mercato del Lavoro
2007
Okun’s law turns out from the relationship between economic growth and unemployment fluctuations of the American economy during the sixties. Following Okun’s conclusions several analysis tried to test the empirical relevance of the initial relation for different countries and historical periods. In this paper we propose an empirical application regarding Italian regions. As we have observed the inconsistency of Okun’s Law for the south of Italy, we tried to test the reason for the absence of significance in the analysed coefficients. Observing the particularly low levels of participation to labour market in this area, we propose other labour market indicators more compatible with a delayed …
Nanocrystal memories for FLASH device applications
2004
Nanocrystals memory cells, in which the conventional polysilicon floating gate is replaced by an array of silicon nanocrystals, have been fabricated and characterized. Single cells and cell arrays of 1 Mb and 10 k have been realized by using a conventional 0.15 μm FLASH technology. Si nanocrystals are deposited on top of tunnel oxide by chemical vapor deposition. Properties of the memory cell have been investigated both for NAND and NOR applications in terms of program/erase window and programming times. Suitable program/erase threshold voltage window can be achieved with fast voltage pulses by adequate choice of tunnel and control dielectric. The feasibility of dual bit storage is also pro…
Radiation effects in nitride read-only memories
2010
Abstract We report on the influence of different types of radiation on the nitride read-only memories (NROM®). The memory cells were irradiated by light ions (Boron), X-rays and γ-rays. Memory transistor parameters, such as threshold voltage and subthreshold drain leakage were studied as a function of the accumulated radiation dose and compared to the as-programmed (-erased) devices parameters. Their time evolution was registered in the range from few hours up to 5 months after the irradiation. The NROM® cells showed good radiation robustness up to high accumulated doses. Sufficient program margin (difference of threshold voltage in the programmed state and the read-out voltage level) remai…
Improvement of the P/E window in nanocrystal memories by the use of high-k materials in the control dielectric
2005
Abstract In this paper nanocrystals memories program curves are shown and their saturation points (steady state condition) can be observed. We present a model that relates the voltage shift at the steady state ( Δ V T ss ) to the gate program voltage (VG). Starting from a good agreement between experimental data and simulations for nanocrystals memory cells with a conventional dielectric structure (SiO2), we present the estimated values of the Δ V T ss vs VG for different control stacks. Our investigation shows an improvement if a material with a high dielectric constant and a small conduction band-offset with respect to the SiO2, is placed between two SiO2 layers when the first of them is …
Peculiar aspects of nanocrystal memory cells: Data and extrapolations
2003
Nanocrystal memory cell are a promising candidate for the scaling of nonvolatile memories in which the conventional floating gate is replaced by an array of nanocrystals. The aim of this paper is to present the results of a thorough investigation of the possibilities and the limitations of such new memory cell. In particular, we focus on devices characterized by a very thin tunnel oxide layer and by silicon nanocrystals formed by chemical vapor deposition. The direct tunneling of the electrons through the tunnel oxide, their storage into the silicon nanocrystals, and furthermore, retention, endurance, and drain turn-on effects, well-known issues for nonvolatile memories, are all investigate…
Distribution of the threshold voltage window in nanocrystal memories with Si dots formed by chemical vapor deposition: Effect of partial self-ordering
2004
Non volatile memories based on Si nanocrystals (Si-ncs) offer an important alternative to conventional floating gate devices, for the numerous potential advantages associated with the discrete-trap structures [1]. Isolated Si-ncs can be obtained by chemical vapor deposition (CVD) through a fully compatible CMOS process. So far, the main limitation for scaling the CVD Si-nc memories at sub-90 nm node is related to the expected fluctuation, from bit to bit, in the device threshold voltage (VTH), due to the spread in the sur- face fraction (Rdot) covered with Si dots [2]. The reason is the assumption that the dot position and the relative distance are fully random. It will be shown that the nu…
Multi-bit storage through Si nanocrystals embedded in SiO2
2004
We have realized Si nanocrystal memory cells in which the Si dots have been deposited by CVD on SiO2 and then covered by a CVD control oxide. In this paper, we report a study on the potential of these cells for dual bit storage. © 2004 Elsevier B.V. All rights reserved.
Memory effects in MOS devices based on Si quantum dots
2003
Silicon quantum dots have been deposited on top of a 3-nm tunnel oxide by Low Pressure Chemical Vapour Deposition (LPCVD) and coated with a 7-nm Chemical Vapour Deposited (CVD) oxide. This stack was then incorporated in Metal-Oxide-Semiconductor structure and used as floating gate of a memory cell. The presence of 3 nm of tunnel oxides allows the injection of the charge by direct tunnel (DT) using low voltages for both program and erase operations. The charge stored in the quantum dots is able to produce a well-detectable flat band shift in the capacitors or, equivalently, a threshold voltage shift in the transistors. Furthermore, due to the presence of SiO 2 between the grains, the lateral…
How far will Silicon nanocrystals push the scaling limits of NVMs technologies?
2004
For the first time, memory devices with optimized high density (2E12#/cm/sup 2/) LPCVD Si nanocrystals have been reproducibly achieved and studied on an extensive statistical basis (from single cell up to 1 Mb test-array) under different programming conditions. An original experimental and theoretical analysis of the threshold voltage shift distribution shows that Si nanocrystals have serious potential to push the scaling of NOR and NAND flash at least to the 35 nm and 65 nm nodes, respectively.
Effects of partial self-ordering of Si dots formed by chemical vapor deposition on the threshold voltage window distribution of Si nanocrystal memori…
2006
We study the role that the denuded zone around Si nanocrystals obtained by chemical vapor deposition plays on the fluctuations of the dot surface coverage. In fact, the capture mechanism of the silicon adatoms in the proximity of existing dots restricts the number of possible nucleation sites, the final dot size, and the dot position, thus driving the process toward partial self-order. We numerically evaluate the relative dispersion of surface coverage for several gate areas and compare the results to the fully random case. The coverage dispersion is related to the fluctuations from bit to bit of the threshold voltage window (Δ Vth) distribution of nanocrystal memories. The evaluations, com…
Localized charge storage in nanocrystal memories: Feasibility of a multi-bit cell
2004
We have realized Si nanocrystal memory cells in which the Si dots have been deposited by chemical vapor deposition (CVD) on the tunnel oxide and then covered by a CVD control oxide. In this paper we report a study on the potential of this type of cells for multi-bit storage. In particular, the possibilities offered by these devices from the point of view of program/erase mechanisms, endurance, and charge retention are shown and discussed.
Threshold Voltage Variability of NROM Memories After Exposure to Ionizing Radiation
2012
Threshold voltage (V-th) behavior of nitride readonly memories (NROMs) was studied after irradiation with photons (gamma-and X-rays), light and heavy ions. Both programmed and nonprogrammed single cells were investigated. The data suggest that two main physical phenomena are contributing to V-th variation and that the V-th loss and the variability can be modeled by a Weibull statistics with a shape parameter k similar to 2.2 regardless of the irradiation species and total dose. The same peculiarities were found in large memory arrays, confirming the results from single-cell studies but with significantly larger statistics. Hence, once the irradiation dose is known, the V-th loss distributio…
Programming options for nanocrystal MOS memories
2003
Nanocrystal memories represent a promising candidate for the scaling of FLASH memories. In these devices, the charge is not stored in a continuous floating gate but in a discontinuous layer composed by numerous discrete silicon quantum dots well separated one from the other.The nanocrystals of radius of few nanometers are realized by chemical vapor deposition (CVD) of silicon on the tunnel oxide of 2.8 nm of thickness. These islands have been coated with a control oxide of 7 nm formed by CVD and incorporated in Metal-Oxide-Semiconductor structure. The devices are programmed and erased by tunnelling using low voltages and fast times. In addition, the programming can be easily achieved also b…
Radiation tolerance of NROM embedded products
2010
Radiation tolerance of NROM memories is demonstrated at the level of industrial 4 Mbit memory embedded modules, specifically not designed for operation in radiation harsh environments. The memory fabricated in 0.18 um technology remains fully functional after total ionization doses exceeding 100 krad. The tests were performed by irradiating with γ-rays (60Co source) and 10 MeV 11B ions in active (during programming/erase and read-out) and passive (no bias) modes. Comprehensive statistics were obtained by using large memory arrays and comparison of the data with the parameters of irradiated single cells allowed deep understanding of the physical phenomena in the irradiated NROM devices for b…