0000000000008990
AUTHOR
Cosimo Gerardi
showing 25 related works from this author
Reliability and Retention Study of Nanocrystal Cell Array
2002
We have studied nanocrystal memory arrays with 2.56 × 105 cells (256kb) in which Si nanocrystals have been obtained by CVD deposition on a 4nm tunnel oxide. The cells in the array are programmed and erased by electron tunneling through the SiO2 dielectric. We find that the threshold voltage distribution has little spread. In addition the arrays are also very robust with respect to drain stress and show good retention.
Effect of high-k materials in the control dielectric stack of nanocrystal memories
2004
In this paper we studied program/erase characteristics by FN tunneling in Si nanocrystal memories. Starting from a very good agreement between experimental data and simulations in the case of a memory cell with a thin tunnel oxide, Silicon dots as medium for charge storage, and a CVD silicon dioxide used as control dielectric, we present estimated values of the charge trapping when a high-k material is present in the control dielectric. We then show preliminary results of nanocrystal memories with control dielectric containing high-k materials. ©2004 IEEE.
Nanocrystal metal-oxide-semiconductor memories obtained by chemical vapor deposition of Si nanocrystals
2002
We have realized nanocrystal memories by using silicon quantum dots embedded in silicon dioxide. The Si dots with the size of few nanometers have been obtained by chemical vapor deposition on very thin tunnel oxides and subsequently coated with a deposited SiO2 control dielectric. A range of temperatures in which we can adequately control a nucleation process, that gives rise to nanocrystal densities of ∼3×1011 cm−2 with good uniformity on the wafer, has been defined. The memory effects are observed in metal-oxide-semiconductor capacitors or field effect transistors by significant and reversible flat band or threshold voltage shifts between written and erased states that can be achieved by …
Nanocrystal MOS with silicon-rich oxide
2001
By electrical measurements we investigate the charge trapping and the charge transport in MOS capacitors in which the gate oxide has been replaced with a silicon rich oxide (SRO) film sandwiched between two thin SiO2 layers.
Nanocrystal memories for FLASH device applications
2004
Nanocrystals memory cells, in which the conventional polysilicon floating gate is replaced by an array of silicon nanocrystals, have been fabricated and characterized. Single cells and cell arrays of 1 Mb and 10 k have been realized by using a conventional 0.15 μm FLASH technology. Si nanocrystals are deposited on top of tunnel oxide by chemical vapor deposition. Properties of the memory cell have been investigated both for NAND and NOR applications in terms of program/erase window and programming times. Suitable program/erase threshold voltage window can be achieved with fast voltage pulses by adequate choice of tunnel and control dielectric. The feasibility of dual bit storage is also pro…
Memory effects in MOS capacitors with silicon rich oxide insulators
2000
ABSTRACTTo form crystalline Si dots embedded in SiO2, we have deposited thin films of silicon rich oxide (SRO) by plasma-enhanced chemical vapor deposition of SiH4 and O2. Then the materials wereannealed in N2 ambient at temperatures between 950 and 1100 °C. Under such processing, the supersaturation of Si in the amorphous SRO film produces the formation of crystalline Si dots embedded in SiO2. The narrow dot size distributions, analyzed by transmission electron microscopy, are characterized by average grain radii and standard deviations down to about 1 nm. The memory function of such structures has been investigated in metal-oxidesemiconductor (MOS) capacitors with a SRO film sandwiched be…
Improvement of the P/E window in nanocrystal memories by the use of high-k materials in the control dielectric
2005
Abstract In this paper nanocrystals memories program curves are shown and their saturation points (steady state condition) can be observed. We present a model that relates the voltage shift at the steady state ( Δ V T ss ) to the gate program voltage (VG). Starting from a good agreement between experimental data and simulations for nanocrystals memory cells with a conventional dielectric structure (SiO2), we present the estimated values of the Δ V T ss vs VG for different control stacks. Our investigation shows an improvement if a material with a high dielectric constant and a small conduction band-offset with respect to the SiO2, is placed between two SiO2 layers when the first of them is …
Memory effects in MOS capacitors with silicon quantum dots
2001
To form crystalline Si dots embedded in SiO2, we have deposited thin films of silicon-rich oxide (SRO) by plasma-enhanced chemical vapor deposition of SiH4 and O2. Then the materials have been annealed in N2 ambient at temperatures between 950°C and 1100°C. Under such processing, the supersaturation of Si in the amorphous SRO film produces the formation of crystalline Si dots embedded in SiO2. The narrow dot size distributions, analyzed by transmission electron microscopy, are characterized by average grain radii and standard deviations down to about 1 nm. The memory functions of such structures has been investigated in MOS capacitors with a SRO film sandwiched between two thin SiO2 layers …
Electrical and structural characterization of metal-oxide-semiconductor capacitors with silicon rich oxide
2001
Metal-oxide-semiconductor capacitors in which the gate oxide has been replaced with a silicon rich oxide (SRO) film sandwiched between two thin SiO2 layers are presented and investigated by transmission electron microscopy and electrical measurements. The grain size distribution and the amount of crystallized silicon remaining in SRO after annealing have been studied by transmission electron microscopy, whereas the charge trapping and the charge transport through the dots in the SRO layer have been extensively investigated by electrical measurements. Furthermore, a model, which explains the electrical behavior of such SRO capacitors, is presented and discussed. © 2001 American Institute of …
Plasmonic modes in molybdenum ultra-thin films suitable for hydrogenated amorphous silicon thin film solar cells
2014
We have recently demonstrated that molybdenum ultra-thin films interposed between hydrogenated amorphous silicon (a-Si:H) and SnO2:F transparent conductive oxide (TCO) in thin film solar cells show light trapping effects which enhance the solar cells performances. The effect of this improvement may be attributed to surface plasmon polariton (SPP) modes excited at the molybdenum interface by the solar radiation. In this paper we show direct evidence of such SPP modes in the case of the molybdenum/air interface by using the attenuated total reflection (ATR) technique, pioneered by Kretschmann, and we evaluate the dielectric constant of molybdenum at 660 nm. (C) 2013 The Authors. Published by …
Location of holes in silicon-rich oxide as memory states
2002
The induced changes of the flatband voltage by the location of holes in a silicon-rich oxide (SRO) film sandwiched between two thin SiO 2 layers [used as gate dielectric in a metal-oxide-semiconductor (MOS) capacitor] can be used as the two states of a memory cell. The principle of operation is based on holes permanently trapped in the SRO layer and reversibly moved up and down, close to the metal and the semiconductor, in order to obtain the two logic states of the memory. The concept has been verified by suitable experiments on MOS structures. The device exhibits an excellent endurance behavior and, due to the low mobility of the holes at low field in the SRO layer, a much longer refresh …
Peculiar aspects of nanocrystal memory cells: Data and extrapolations
2003
Nanocrystal memory cell are a promising candidate for the scaling of nonvolatile memories in which the conventional floating gate is replaced by an array of nanocrystals. The aim of this paper is to present the results of a thorough investigation of the possibilities and the limitations of such new memory cell. In particular, we focus on devices characterized by a very thin tunnel oxide layer and by silicon nanocrystals formed by chemical vapor deposition. The direct tunneling of the electrons through the tunnel oxide, their storage into the silicon nanocrystals, and furthermore, retention, endurance, and drain turn-on effects, well-known issues for nonvolatile memories, are all investigate…
Reduction of thermal damage in ultrathin gate oxides after intrinsic dielectric breakdown
2001
We have compared the thermal damage in ultrathin gate SiO2 layers of 5.6 and 3 nm thickness after intrinsic dielectric breakdown due to constant voltage Fowler-Nordheim stress. The power dissipated through the metal-oxide-semiconductor capacitor during the breakdown transient, measured with high time resolution, strongly decreases with oxide thickness. This is reflected in a noticeable reduction of the thermal damage found in the structure after breakdown. The effect can be explained as the consequence of the lower amount of defects present in the oxide at the breakdown instant and of the occurrence of a softer breakdown in the initial spot. The present data allow us to estimate the power t…
Plasmonic effects of ultra-thin Mo films on hydrogenated amorphous Si photovoltaic cells
2012
We report on the improvement of short circuit current (JSC), fill factor (FF), and open circuit resistance (ROC) in hydrogenated amorphous silicon (a-Si:H) photovoltaic cells with a p-type/intrinsic/n-type structure, achieved by the addition of an ultra-thin molybdenum film between the p-type film and the transparent conductive oxide/glass substrate. For suitable conditions, improvements of ≈10% in average internal quantum efficiency and up to 5%–10% under standard illumination in JSC, FF, and ROC are observed. These are attributed to the excitation of surface plasmon polariton modes of the a-Si:H/Mo interface.
Electrical characterization of highefficiency bifacial silicon solar cells
2018
This work presents a preliminary study on the electrical characterization of high efficiency bifacial solar cells. An opening discussion on the state-of-the-art of such advanced technology is initially proposed and the experimental characterization of some prototypes is described. From this analysis, it can be stated that the bifacial silicon solar cells can be a very promising technology with high electrical performances and efficiency.
Multi-bit storage through Si nanocrystals embedded in SiO2
2004
We have realized Si nanocrystal memory cells in which the Si dots have been deposited by CVD on SiO2 and then covered by a CVD control oxide. In this paper, we report a study on the potential of these cells for dual bit storage. © 2004 Elsevier B.V. All rights reserved.
Memory effects in MOS devices based on Si quantum dots
2003
Silicon quantum dots have been deposited on top of a 3-nm tunnel oxide by Low Pressure Chemical Vapour Deposition (LPCVD) and coated with a 7-nm Chemical Vapour Deposited (CVD) oxide. This stack was then incorporated in Metal-Oxide-Semiconductor structure and used as floating gate of a memory cell. The presence of 3 nm of tunnel oxides allows the injection of the charge by direct tunnel (DT) using low voltages for both program and erase operations. The charge stored in the quantum dots is able to produce a well-detectable flat band shift in the capacitors or, equivalently, a threshold voltage shift in the transistors. Furthermore, due to the presence of SiO 2 between the grains, the lateral…
How far will Silicon nanocrystals push the scaling limits of NVMs technologies?
2004
For the first time, memory devices with optimized high density (2E12#/cm/sup 2/) LPCVD Si nanocrystals have been reproducibly achieved and studied on an extensive statistical basis (from single cell up to 1 Mb test-array) under different programming conditions. An original experimental and theoretical analysis of the threshold voltage shift distribution shows that Si nanocrystals have serious potential to push the scaling of NOR and NAND flash at least to the 35 nm and 65 nm nodes, respectively.
Memory effects in single-electron nanostructures
2001
We investigate the memory function at room temperature in devices based on quantum dots. By Low Pressure Chemical Vapour Deposition (LPCVD) we deposited Si dots embedded in SiO2. On these devices flat band voltage shifts were well detected at low write voltages for write times of the order of milliseconds, and furthermore, a plateau in the flat band voltage shift, maybe consequence of Coulomb blockdale, was observed.
Effects of partial self-ordering of Si dots formed by chemical vapor deposition on the threshold voltage window distribution of Si nanocrystal memori…
2006
We study the role that the denuded zone around Si nanocrystals obtained by chemical vapor deposition plays on the fluctuations of the dot surface coverage. In fact, the capture mechanism of the silicon adatoms in the proximity of existing dots restricts the number of possible nucleation sites, the final dot size, and the dot position, thus driving the process toward partial self-order. We numerically evaluate the relative dispersion of surface coverage for several gate areas and compare the results to the fully random case. The coverage dispersion is related to the fluctuations from bit to bit of the threshold voltage window (Δ Vth) distribution of nanocrystal memories. The evaluations, com…
Localized charge storage in nanocrystal memories: Feasibility of a multi-bit cell
2004
We have realized Si nanocrystal memory cells in which the Si dots have been deposited by chemical vapor deposition (CVD) on the tunnel oxide and then covered by a CVD control oxide. In this paper we report a study on the potential of this type of cells for multi-bit storage. In particular, the possibilities offered by these devices from the point of view of program/erase mechanisms, endurance, and charge retention are shown and discussed.
Role of the Back Metal-Semiconductor Contact on the Performances of a-Si:H Solar Cells
2011
We have investigated the role of the metal-semiconductor back contact on the performances of thin film modules consisting of single junction a-Si:H photovoltaic (PV) cells deposited with p-i-n configuration. We find that an adequate choice of the back contact helps reducing the barrier height of the junction improving the contact conductivity. For this purpose Mo has shown to be effective. Moreover we find that Mo, as refractory material, has additional beneficial effects reducing the formation of defects leading to the decrease of recombination losses. We have then fabricated a PV module on flexible substrate for indoor energy harvesting applications using Mo as back contact. An efficiency…
Programming options for nanocrystal MOS memories
2003
Nanocrystal memories represent a promising candidate for the scaling of FLASH memories. In these devices, the charge is not stored in a continuous floating gate but in a discontinuous layer composed by numerous discrete silicon quantum dots well separated one from the other.The nanocrystals of radius of few nanometers are realized by chemical vapor deposition (CVD) of silicon on the tunnel oxide of 2.8 nm of thickness. These islands have been coated with a control oxide of 7 nm formed by CVD and incorporated in Metal-Oxide-Semiconductor structure. The devices are programmed and erased by tunnelling using low voltages and fast times. In addition, the programming can be easily achieved also b…
Nanocrystal MOS memories obtained by LPCVD deposition of Si nanograins
2001
We have realized silicon quantum dots embedded in SiO2 which act as nano-floating gates of MOS memories. The dots with nanometer sizes have been deposited by LPCVD on a 3nm tunnel oxide. Two processes at a fixed pressure have been explored by varying the temperature. SiH4 with a N2 carrier gas have been used in the former case, SiH4 and H2 have been used in the latter. In both cases a nanocrystalline silicon layer is obtained, with nanocrystals a density higher than 1011 cm-2. The process with H2 carrier gas is more controllable and leads to the formation of nanocrystals with a more regular shape. In both cases the density of grains is able to originate detectable threshold shifts in the me…
Comparison between textured SnO2:F and Mo contacts with the p-type layer in p–i–n hydrogenate amorphous silicon solar cells by forward bias impedance…
2013
Abstract In this paper we compare the performance of the textured SnO2:F and Mo contacts with the p-type layer in p–i–n hydrogenate amorphous silicon (a-Si:H) solar cells. We use standard current–voltage (I–V) electrical characterization methods coupled with forward bias small signal impedance analysis. We show the efficacy of this technique to determine the effective carrier lifetime in photovoltaic cells. We show that such effective lifetimes are indeed directly connected to the respective dark diode saturation currents. We also find that the effective lifetime is constant with the temperature in the 0–70 °C range and it is significantly better for the solar cell with Mo diode contact. Th…